CMOS ASIC Design of Multi-frequency Multi-constellation GNSS Front-ends

With the emergence of the new global navigation satellite systems (GNSSs) such as Galileo, COMPASS and GLONASS, the US Global Positioning System (GPS) has new competitors. This multiplicity of constellations will offer new services and a much better satellite coverage. Public regulated service (PRS) is one of these new services that Galileo, the first global positioning service under civilian control, will offers. The PRS is a proprietary encrypted navigation designed to be more reliable and robust against jamming and provides premium quality in terms of position and timing and continuity of service, but it requires the use of FEs with extended capabilities. The project that this thesis starts from, aims to develop a dual frequency (E1 and E6) PRS receiver with a focus on a solution for professional applications that combines affordability and robustness. To limit the production cost, the choice of a monolithic design in a multi-purpose 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology have been selected, and to reduce the susceptibility to interference, the targeted receiver is composed of two independent FEs. The first ASIC described here is such FEs bundle. Each FE is composed of a radio frequency (RF) chain that includes a low-noise amplifier (LNA), a quadrature mixer, a frequency synthesizer (FS), two intermediate frequency (IF) filters, two variable-gain amplifiers (VGAs) and two 6-bit flash analog-to-digital converters (ADCs). Each have an IF bandwidth of 50 MHz to accommodate the wide-band PRS signals. The FE achieves a 30 dB of dynamic gain control at each channel. The complete receivers occupies a die area of 11.5 mm2 while consuming 115 mW from a supply of a 1.8 V. The second ASIC that targets civilian applications, is a reconfigurable single-channel FE that permits to exploit the interoperability among GNSSs. The FE can operate in two modes: a ¿narrow-band mode¿, dedicated to Beidou-B1 with an IF bandwidth of 8 MHz, and a ¿wide-band mode¿ with an IF bandwidth of 23 MHz, which can accommodate simultaneous reception of Beidou-B1/GPS-L1/Galileo-E1. These two modes consumes respectively 22.85 mA and 28.45 mA from a 1.8 V supply. Developed with the best linearity in mind, the FE shows very good linearity with an input-referred 1 dB compression point (IP1dB) of better than -27.6 dBm. The FE gain is stepwise flexible from 39 dB and to a maximum of 58 dB. The complete FE occupies a die area of only 2.6 mm2 in a 0.18 µm CMOS. To also accommodate the wide-band PRS signals in the IF section of the FE, a highly selective wide-tuning-range 4th-order Gm-C elliptic low-pass filter is used. It features an innovative continuous tuning circuit that adjusts the bias current of the Gm cell¿s input stage to control the cutoff frequency. With this circuit, the power consumption is proportional to the cutoff frequency thus the power efficiency is achieved while keeping the linearity near constant. Thanks to a Gm switching technique, which permit to keep the signal path switchless, the filter shows an extended tuning of the cutoff frequency that covers continuously a range from 7.4 MHz to 27.4 MHz. Moreover the abrupt roll-off of up to 66 dB/octave, can mitigate out-of-band interference. The filter consumes 2.1 mA and 7.5 mA at its lowest and highest cutoff frequencies respectively, and its active area occupies, 0.23 mm2. It achieves a high input-referred third-order intercept point (IIP3) of up to -1.3 dBVRMS

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Microwave and Millimeter-wave Concurrent Multiband Low-Noise Amplifiers and Receiver Front-end in SiGe BiCMOS Technology

A fully integrated SiGe BiCMOS concurrent multiband receiver front-end and its building blocks including multiband low-noise amplifiers (LNAs), single-to-differential amplifiers and mixer are presented for various Ku-/K-/Ka-band applications. The proposed concurrent multiband receiver building blocks and receiver front-end achieve the best stopband rejection performances as compared to the existing multiband LNAs and receivers. First, a novel feedback tri-band load composed of two inductor feedback notch filters is proposed to overcome the low Q-factor of integrated passive inductors, and hence it provides superior stopband rejection ratio (SRR). A new 13.5/24/35-GHz concurrent tri-band LNA implementing the feedback tri-band load is presented. The developed tri-band LNA is the first concurrent tri-band LNA operating up to millimeter-wave region. By expanding the operating principle of the feedback tri-band load, a 21.5/36.5-GHz concurrent dual-band LNA with an inductor feedback dual-band load and another 23/36-GHz concurrent dual-band LNA with a new transformer feedback dual-band load are also presented. The latter provides more degrees of freedom for the creation of the stopband and passbands as compared to the former. A 22/36-GHz concurrent dual-band single-to-differential LNA employing a novel single-to-differential transformer feedback dual-band load is presented. The developed LNA is the first true concurrent dual-band single-to-differential amplifier. A novel 24.5/36.5 GHz concurrent dual-band merged single-to-differential LNA and mixer implementing the proposed single-to-differential transformer feedback dual-band load is also presented. With a 21-GHz LO signal, the down-converted dual IF bands are located at 3.5/15.5 GHz for two passband signals at 24.5/36.5 GHz, respectively. The proposed merged LNA and mixer is the first fully integrated concurrent dual-band mixer operating up to millimeter-wave frequencies without using any switching mechanism. Finally, a 24.5/36.5-GHz concurrent dual-band receiver front-end is proposed. It consists of the developed concurrent dual-band LNA using the single-to-single transformer feedback dual-band load and the developed concurrent dual-band merged LNA and mixer employing the single-to-differential transformer feedback dual-band load. The developed concurrent dual-band receiver front-end achieves the highest gain and the best NF performances with the largest SRRs, while operating at highest frequencies up to millimeter-wave region, among the concurrent dual-band receivers reported to date

Projeto e caracterização de amplificadores de baixo ruído em 2,4 ghz

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Engenharia ElétricaEsta dissertação está centrada em amplificadores de baixo ruído (LNAs) e pode ser dividida em três partes. Na primeira parte é feita uma introdução de LNAs em tecnologia CMOS que é seguida por um levantamento do estado da arte desses amplificadores. Na segunda parte deste trabalho é feita uma revisão sobre figura de ruído cuja definição é válida para um sistema, circuito ou dispositivo. Após essa revisão apresenta-se uma análise da figura de ruído em quadripolos em que são derivadas equações usadas em projetos de LNAs, mostra-se também o método Y usado para caracterização da figura de ruído de um quadripolo qualquer. Após esse estudo finaliza-se a segunda parte da dissertação com um estudo de caso sobre medidas on-chip usando um transistor. Na última parte da dissertação apresenta-se o LNA em um sistema de recepção de sinais, logo em seguida são mostradas duas configurações básicas para amplificadores: a configuração do transistor de entrada configurado em fonte comum e outra com configuração em porta comum. Dessa forma, a fim de introduzir o leitor no projeto de LNAs, são derivados os parâmetros básicos de desempenho desses amplificadores para cada configuração do transistor de entrada mostrada. Após essa etapa, com intuito de validar os conceitos aprendidos, são projetados três LNAs com comprimento de canal de 0,18 mm e com especificações distintas. Um LNA possui restrição de tensão, outro tem restrição de consumo e o último amplificador é projetado especialmente para operar em um receptor ZigBee . São apresentados também os resultados experimentais dos LNAs com restrição de tensão e consumo.This dissertation is centered in low noise amplifiers (LNAs) and it can be divided in three parts. In the first part it is made an introduction of LNAs in a CMOS technology and it is followed by a study of the state-of-art of these amplifiers. In the second part of this work it is done a review on noise figure whose definition is valid for a system, circuit or device. After this review it is presented a noise figure analysis in fourpoles which the derived equations are used in LNA#s design, it is also shown the Y-factor method for noise figure extraction of any fourpole. Thereafter the second part is finished with a case of study about on chip measurements using a transistor. In the last part of the dissertation it is presented a LNA placed in a signal receiver system, then it is shown two amplifiers basic configurations: a configuration using the input transistor in common source and a second one using it in a common gate configuration. Thereby, with means to introduce the reader on LNA's design, the basic parameters of performance of these amplifiers are derived for each shown configuration of the input transistor. Hereafter, with means to validate the learned concepts, it is designed three LNAs with channel length of 0,18mm and with different specifications. One LNA has voltage restrictions, another has a power consumption restriction and the last amplifier is designed specially to operate in a ZigBee receiver. It is also presented the voltage and power restricted LNA's experimental results

Test bench solutions for advanced GNSS receivers : implementation, automation, and application

Considerable study has been devoted to the implementation of GNSS receivers for diverse applications, and to finding solutions to some of the non-idealities associated with such receivers. However, not much research is devoted to innovations in their performance evaluation, even though this is an integral step in the overall implementation process. This research work attempts to address this issue through three different perspectives: by focusing on innovation in the testing procedures and test-bench implementation, its automation and its application to advanced multi-frequency, multi-constellation GPS and Galileo receivers. Majority of this research was conducted within the GREAT, GRAMMAR, and FUGAT projects funded by EU FP6/FP7 and TEKES respectively, during which the author was responsible for designing test-scenarios and performing validations of the implemented receiver solution. The first part of the research is devoted to the study and design of sources of test signals for an advanced GNSS receiver test-bench. An in-depth background literature study was conducted on software-based GNSS signal simulators to trace their evolution over the past two decades. Keeping their special features and limitations in view, recommendations have been made on the optimum architecture and essential features within such simulators for testing of advanced receivers. This resulted in the implementation of an experimental software-based simulator capable of producing GPS L1 and Galileo E1 signals at intermediate frequency. Another solution investigated was a GNSS Sampled Data Generator (SDG) based on wideband sampling. This included designing the entire radio front-end operating on the bandpass-sampling principle. The low noise amplifier designed as part of this SDG has been implemented on a printed circuit board. Phase noise (PN) from the radio front-end’s local frequency generator (LFG) is a source of error that has hitherto not been included in any GNSS signal simulator. Furthermore, the characterization of the baseband tracking loops in presence of this phase noise has not yet been included in the typical receiver test scenarios. The second part of this research attempts to create mathematical models representing the LFG’s phase noise contribution, first for a free running oscillator and later for a complete phase-locked loop (PLL). The effect of such phase noise was studied on the baseband correlation performance of GPS and Galileo receivers. The results helped to demonstrate a direct relation between the PN and the baseband tracking performance, thus helping to define guidelines for radio front-end PLL circuit design in order to maintain a minimum baseband tracking performance within the GNSS receiver. The final part of this research work focusses on describing the automated test-bench developed at Tampere University of Technology (TUT) for analyzing the overall performance of multi-frequency multi-constellation GNSS receivers. The proposed testbench includes a data capture tool to extract internal process information, and the overall controlling software, called automated performance evaluation tool, that is able to communicate between all modules for hands-free, one-button-click testing of GNSS receivers. Furthermore, these tools have been applied for the single frequency GPS L1 performance testing of the TUTGNSS receiver, with recommendations on how they can be adapted to testing of advanced multi-frequency, multi-constellation receivers