Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Silicon on Ferroelectric Insulator Field Effect Transistor (SOFFET): A Radical Alternative to Overcome the Thermionic Limit

Title from PDF of title page viewed January 3,2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 165-180)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2016The path of down-scaling traditional MOSFET is reaching its technological, economic and, most importantly, fundamental physical limits. Before the dead-end of the roadmap, it is imperative to conduct a broad research to find alternative materials and new architectures to the current technology for the MOSFET devices. Beyond silicon electronic materials like group III-V heterostructure, ferroelectric material, carbon nanotubes (CNTs), and other nanowire-based designs are in development to become the core technology for non-classical CMOS structures. Field effect transistors (FETs) in general have made unprecedented progress in the last few decades by down-scaling device dimensions and power supply level leading to extremely high numbers of devices in a single chip. High density integrated circuits are now facing major challenges related to power management and heat dissipation due to excessive leakage, mainly due to subthreshold conduction. Over the years, planar MOSFET dimensional reduction was the only process followed by the semiconductor industry to improve device performance and to reduce the power supply. Further scaling increases short-channel-effect (SCE), and off-state current makes it difficult for the industry to follow the well-known Moore’s Law with bulk devices. Therefore, scaling planar MOSFET is no longer considered as a feasible solution to extend this law. The down-scaling of metal-oxide-semiconductor field effect transistors (MOSFETs) leads to severe short-channel-effects and power leakage at large-scale integrated circuits (LSIs). The device, which is governed by the thermionic emission of the carriers injected from the source to the channel region, has set a limitation of the subthreshold swing (S) of 60 / at room temperature. Devices with ‘S’ below this limit is highly desirable to reduce the power consumption and maintaining a high / current ratio. Therefore, the future of semiconductor industry hangs on new architectures, new materials or even new physics to govern the flow of carriers in new switches. As the subthreshold swing is increasing at every technology node, new structures using SOI, multi-gate, nanowire approach, and new channel materials such as III–V semiconductor have not satisfied the targeted values of subthreshold swing. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic emission limit of 60 /. This value was unbreakable by the new structure (SOI FinFET). On the other hand, most of the preview proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for sub-60 mV/decade designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This dissertation also proposes a novel design that exploits the concept of negative capacitance. The new field-effect-transistor (FET) based on ferroelectric insulator named Silicon-On-Ferroelectric Insulator Field effect-transistor (SOFFET). This proposal is a promising methodology for future ultra low-power applications because it demonstrates the ability to replace the silicon-bulk based MOSFET, and offers a subthreshold swing significantly lower than 60 / and reduced threshold voltage to form a conducting channel. The proposed SOFFET design, which utilizes the negative capacitance of a ferroelectric insulator in the body-stack, is completely different from the FeFET and NCFET designs. In addition to having the NC effect, the proposed device will have all the advantages of an SOI device. Body-stack that we are intending in this research has many advantages over the gate-stack. First, it is more compatible with the existing processes. Second, the gate and the working area of the proposed SOFFET is like the planar MOSFET. Third, the complexity and ferroelectric material interferences are shifted to the body of the device from the gate and the working area. The proposed structure offers better scalability and superior constructability because of the high-dielectric buried insulator. Here we are providing a very simplified model for the structure. Silicon-on-ferroelectric leads to several advantages including low off-state current and shift in the threshold voltage with the decrease of the ferroelectric material thickness. Moreover, having an insulator in the body of the device increases the controllability over the channel, which leads to the reduction in the short-channel-effect (SCE). The proposed SOFFET offers low value of subthreshold swing (S) leading to better performance in the on-state. The off-state current is directly related to S. So, the off-state current is also minimum in the proposed structure.Introduction -- Subthreshold swing -- Multi-gate devices -- Tunneling field effect transistors -- I-mos & FET transistors -- Ferroelectric based field effect transistors -- An analytical model to approximate the subthreshold swing for SOI-FINFET -- Multichannel tunneling carbon nanotube FET -- Partially depleted silicon-on-Ferroelectric insulator FET -- Fully depleted silicon-on-ferroelectric insulator FET -- Advantages, manufacturing process, and future work of the proposed devices -- Appendix A. Estimation of the body factor (n) [eta] of SOI FinFET -- Appendix B. Solution for the Poisson Equation of MT-CNTFE