107 research outputs found
Low Voltage Low Power Analogue Circuits Design
DisertaÄnĂ prĂĄce je zamÄĆena na vĂœzkum nejbÄĆŸnÄjĆĄĂch metod, kterĂ© se vyuĆŸĂvajĂ pĆi nĂĄvrhu analogovĂœch obvodĆŻ s vyuĆŸitĂ nĂzkonapÄĆ„ovĂœch (LV) a nĂzkopĆĂkonovĂœch (LP) struktur. Tyto LV LP obvody mohou bĂœt vytvoĆeny dĂky vyspÄlĂœm technologiĂm nebo takĂ© vyuĆŸitĂm pokroÄilĂœch technik nĂĄvrhu. DisertaÄnĂ prĂĄce se zabĂœvĂĄ prĂĄvÄ pokroÄilĂœmi technikami nĂĄvrhu, pĆedevĆĄĂm pak nekonvenÄnĂmi. Mezi tyto techniky patĆĂ vyuĆŸitĂ prvkĆŻ s ĆĂzenĂœm substrĂĄtem (bulk-driven - BD), s plovoucĂm hradlem (floating-gate - FG), s kvazi plovoucĂm hradlem (quasi-floating-gate - QFG), s ĆĂzenĂœm substrĂĄtem s plovoucĂm hradlem (bulk-driven floating-gate - BD-FG) a s ĆĂzenĂœm substrĂĄtem s kvazi plovoucĂm hradlem (quasi-floating-gate - BD-QFG). PrĂĄce je takĂ© orientovĂĄna na moĆŸnĂ© zpĆŻsoby implementace znĂĄmĂœch a modernĂch aktivnĂch prvkĆŻ pracujĂcĂch v napÄĆ„ovĂ©m, proudovĂ©m nebo mix-mĂłdu. Mezi tyto prvky lze zaÄlenit zesilovaÄe typu OTA (operational transconductance amplifier), CCII (second generation current conveyor), FB-CCII (fully-differential second generation current conveyor), FB-DDA (fully-balanced differential difference amplifier), VDTA (voltage differencing transconductance amplifier), CC-CDBA (current-controlled current differencing buffered amplifier) a CFOA (current feedback operational amplifier). Za ĂșÄelem potvrzenĂ funkÄnosti a chovĂĄnĂ vĂœĆĄe zmĂnÄnĂœch struktur a prvkĆŻ byly vytvoĆeny pĆĂklady aplikacĂ, kterĂ© simulujĂ usmÄrĆovacĂ a induktanÄnĂ vlastnosti diody, dĂĄle pak filtry dolnĂ propusti, pĂĄsmovĂ© propusti a takĂ© univerzĂĄlnĂ filtry. VĆĄechny aktivnĂ prvky a pĆĂklady aplikacĂ byly ovÄĆeny pomocĂ PSpice simulacĂ s vyuĆŸitĂm parametrĆŻ technologie 0,18 m TSMC CMOS. Pro ilustraci pĆesnĂ©ho a ĂșÄinnĂ©ho chovĂĄnĂ struktur je v disertaÄnĂ prĂĄci zahrnuto velkĂ© mnoĆŸstvĂ simulaÄnĂch vĂœsledkĆŻ.The dissertation thesis is aiming at examining the most common methods adopted by analog circuits' designers in order to achieve low voltage (LV) low power (LP) configurations. The capability of LV LP operation could be achieved either by developed technologies or by design techniques. The thesis is concentrating upon design techniques, especially the nonâconventional ones which are bulkâdriven (BD), floatingâgate (FG), quasiâfloatingâgate (QFG), bulkâdriven floatingâgate (BDâFG) and bulkâdriven quasiâfloatingâgate (BDâQFG) techniques. The thesis also looks at ways of implementing structures of wellâknown and modern active elements operating in voltageâ, currentâ, and mixedâmode such as operational transconductance amplifier (OTA), second generation current conveyor (CCII), fullyâdifferential second generation current conveyor (FBâCCII), fullyâbalanced differential difference amplifier (FBâDDA), voltage differencing transconductance amplifier (VDTA), currentâcontrolled current differencing buffered amplifier (CCâCDBA) and current feedback operational amplifier (CFOA). In order to confirm the functionality and behavior of these configurations and elements, they have been utilized in application examples such as diodeâless rectifier and inductance simulations, as well as lowâpass, bandâpass and universal filters. All active elements and application examples have been verified by PSpice simulator using the 0.18 m TSMC CMOS parameters. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of structures.
Conditioning electrical impedance mammography system
A multi-frequency Electrical Impedance Mammography (EIM) system has been developed to evaluate the conductivity and permittivity spectrums of breast tissues, which aims to improve early detection of breast cancer as a non-invasive, relatively low cost and label-free screening (or pre-screening) method. Multi-frequency EIM systems typically employ current excitations and measure differential potentials from the subject under test. Both the output impedance and system performance (SNR and accuracy) depend on the total output resistance, stray and output capacitances, capacitance at the electrode level, crosstalk at the chip and PCB levels. This makes the system design highly complex due to the impact of the unwanted capacitive effects, which substantially reduce the output impedance of stable current sources and bandwidth of the data that can be acquired. To overcome these difficulties, we present new methods to design a high performance, wide bandwidth EIM system using novel second generation current conveyor operational amplifiers based on a gyrator (OCCII-GIC) combination with different current excitation systems to cancel unwanted capacitive effects from the whole system. We reconstructed tomography images using a planar E-phantom consisting of an RSC circuit model, which represents the resistance of extra-cellular (R), intra-cellular (S) and membrane capacitance (C) of the breast tissues to validate the performance of the system. The experimental results demonstrated that an EIM system with the new design achieved a high output impedance of 10MΩ at 1MHz to at least 3MΩ at 3MHz frequency, with an average SNR and modelling accuracy of over 80dB and 99%, respectively
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
Low-Power and Programmable Analog Circuitry for Wireless Sensors
Embedding networks of secure, wirelessly-connected sensors and actuators will help us to conscientiously manage our local and extended environments. One major challenge for this vision is to create networks of wireless sensor devices that provide maximal knowledge of their environment while using only the energy that is available within that environment. In this work, it is argued that the energy constraints in wireless sensor design are best addressed by incorporating analog signal processors. The low power-consumption of an analog signal processor allows persistent monitoring of multiple sensors while the device\u27s analog-to-digital converter, microcontroller, and transceiver are all in sleep mode. This dissertation describes the development of analog signal processing integrated circuits for wireless sensor networks. Specific technology problems that are addressed include reconfigurable processing architectures for low-power sensing applications, as well as the development of reprogrammable biasing for analog circuits
STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS
Microelectronic devices and systems have been extensively utilized in a variety of radiation
environments, ranging from the low-earth orbit to the ground level. A high-energy particle from
such an environment may cause voltage/current transients, thereby inducing Single Event Effect
(SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975,
this community has made tremendous progress in investigating the mechanisms of SEE and
exploring radiation tolerant techniques. However, as the IC technology advances, the existing
hardening techniques have been rendered less effective because of the reduced spacing and
charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has
identified radiation-induced soft errors as the major threat to the reliable operation of electronic
systems in the future. In digital systems, hardening techniques of their core components, such as
latches, logic, and clock network, need to be addressed.
Two single event tolerant latch designs taking advantage of feedback transistors are
presented and evaluated in both single event resilience and overhead. These feedback transistors
are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in
a larger feedback delay and higher single event tolerance. On the other hand, these extra
transistors are turned ON when the cell is in the write mode. As a result, no significant write
delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section
when compared to the reference cells.
Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The
worst case occurs when the output is evaluated logic high, where the pull-up networks are turned
OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail.
A capacitor added to the feedback path increases the node capacitance of the output and the
feedback delay, thereby increasing the single event critical charge. Another differential structure
that has two differential inputs and outputs eliminates single event upset issues at the expense of
an increased number of transistors.
Clock networks in advanced technology nodes may cause significant errors in an IC as the
devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme
in a digital system. It was fabricated in a 28nm technology and evaluated through the use of
heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was
demonstrated during these tests.
In addition to mitigating single event issues by using hardened designs, built-in current
sensors can be used to detect single event induced currents in the n-well and, if implemented,
subsequently execute fault correction actions. These sensors were simulated and fabricated in a
28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of
this sensor design. This manifests itself as an alternative to existing hardening techniques.
In conclusion, this work investigates single event effects in digital systems, especially those
in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock,
and current sensor designs have been presented and evaluated. Through the use of these designs,
the single event tolerance of a digital system can be achieved at the expense of varying overhead
in terms of area, power, and delay
Study of Single-Event Transient Effects on Analog Circuits
Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment.
Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects.
The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance
Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays
Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging
and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through
the skull has prevented ultrasound imaging of the brain. This research is a prime
step toward implantable wireless microsystems that use ultrasound to image the
brain by bypassing the skull. These microsystems offer autonomous scanning
(beam steering and focusing) of the brain and transferring data out of the brain for
further processing and image reconstruction.
The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their
associated integrated electronics in terms of electrical power transfer and acoustic
reflection which would potentially lead to more efficient and high-performance
systems.
A fully wireless architecture for ultrasound imaging is demonstrated for the
first time. An on-chip programmable transmit (TX) beamformer enables phased
array focusing and steering of ultrasound waves in the transmit mode while its
on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB)
uplink transmitter minimizes the effect of path loss on the transmitted image data
out of the brain. A single-chip application-specific integrated circuit (ASIC) is de-
signed to realize the wireless architecture and interface with array elements, each
of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser,
a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building
blocks.
Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a
power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo
differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems.
In addition, the effect of matching and electrical termination on CMUT array
elements is explored leading to new interface structures to improve bandwidth
and sensitivity of CMUT arrays in different operation regions. Comprehensive
analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D
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A high-performance, multi-frequency micro-controlled Electrical Impedance Mammography (EIM) excitation and phantom validation system
The research concentrates on the design, development and calibration of a high performance Electrical Impedance Mammography (EIM) system for early detection of breast cancer at the macro and micro scale (at an early stage applicable for different breast sizes and shapes). The enhancement of the Electrical Impedance Tomography (EIT) system focuses on developing electrical and electronic instrumentations and improving the current source topologies to make them operate at multiple frequencies for the purpose of measuring permittivity and conductivity of different breast tissues. The calibration, assessment systems have employed current calibration in the EIT to evaluate the impedance distribution. This facilitates the acquisition of accurate impedance images to enable images of the internal structure of the breast to be constructed. A constraint on EIT systems is that the current injection system suffers from the effects of stray capacitance having a major impact on the hardware subsystem as the EIT is an ill-posed inverse problem which depends on the noise level in EIT measured data and regularization parameter in the reconstruction algorithm. This research aims are to prevent this problem by using a capacitance cancellation method based on a General Impedance Converter (GIC) implemented by operation of a second generation of current conveyor called OCCII-GIC and calibration methods to facilitate operation in the high frequency range. An EIT system based on a planar 85-electrode channel and using a Microcontroller unit (MCU) for addressing control between 85 electrodes and implementing calibration methods has been constructed. In EIT systems, assessment, validation of the performance and calibration of systematic errors in the electrical field generated inside of the interrogated volume is important. Evaluation of the EIT system will be assessed using a realistic electronic phantom (E-phantom). This enables the evaluation of the different conductivity values of the tissue, which has been created and evaluated based on the RSC circuit model for the different electrical conductivities and electrical impedivities in breast tissue
A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter
The future e + e â collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters.
To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution.
This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The
charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to
meet the stringent power consumption requirement.
This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested
Electronics for Sensors
The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces
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