Low temperature, low pressure CMOS compatible Cu -Cu thermo-compression bonding with Ti passivation for 3D IC integration

In this paper, we report the methodology of achieving low temperature, low pressure CMOS compatible Wafer-on-Wafer (WoW) Cu-Cu thermo-compression bonding using optimally chosen ultra-thin layer of Titanium (Ti) as a passivation layer. We systematically studied the effects of Ti thickness on bonding quality via its effects on surface roughness, oxidation prevention and inter diffusion of Cu. Through this study, we have found that a Ti thickness of 3 nm not only results in excellent bonding but also leads to a reduction in operating pressure to 2.5 bar and temperature to 175° C. The reduction in pressure is more than an order of magnitude lower relative to the current state-of-the-art. The lower operating pressure and temperature manifest themselves in a very good homogenous bond further highlighting the efficacy of our approach. Finally, our results have been corroborated by evidence from AFM study of the Cu/Ti surface prior to bonding. The bond strength of Cu-Cu as measured by Instron Microtester measurement system is found to be 190 MPa which compares very well with the reported literatures

Metal-Alloy Cu Surface Passivation Leads to High Quality Fine-Pitch Bump-Less Cu-Cu Bonding for 3D IC and Heterogeneous Integration Applications

In this paper, we report a low temperature, fine-pitch, bump-less, damascene compatible Cu-Cu thermocompression bonding, using an optimized ultra-thin passivation layer, Constantan, which is an alloy (Copper-Nickel) of 55% Cu and 45% Ni. Surface oxidation and its roughness are the major bottlenecks in achieving high quality, low temperature, and fine-pitch Cu-Cu bonding. In this endeavor, we have used Cu rich alloy (Constantan) for passivation of Cu surface prior to bonding. We have systematically optimized the constantan passivation layer thickness for high quality low temperature, low pressure, bump-less Cu-Cu bonding. Also, we have studied systematically the efficacy of Cu surface passivation with optimized ultra-thin constantan alloy passivation layer. After rigorous trial and optimization, we successfully identified 2 nm passivation layer thickness, at which very high quality Cu-Cu bonding could be accomplished at sub 200 °C with a nominal contact pressure of 0.4 MPa. Post-bonding, electrical and mechanical characterization were validated using four-probe IV measurement and bond strength measurement respectively. Furthermore, Cu-Cu bonding interface was analyzed using IR wafer bonder inspection tool. Very high bond strength of 163 MPa and defect free interface observed by WBI-IR clearly suggests, Cu-Cu finepitch bonding with optimized ultra-thin alloy of 2 nm thick constantan, is of very high quality and reliable. Moreover, this novel bonding approach with alloy based interconnect passivation technique is the prime contestant for future heterogeneous integration

Investigation of Cu‑Cu bonding for 2.5D and 3D system integration using self‑assembled monolayer as oxidation inhibitor

Das Cu-Cu-Bonden ist eine vielversprechende lötfreie Fine-Pitch-Verbindungstechnologie für die 2,5D- und 3D-Systemintegration. Diese Bondtechnologie wurde in den letzten Jahren intensiv untersucht und wird derzeit für miniaturisierte mikroelektronische Produkte eingesetzt. Allerdings, stellt das Cu‑Cu-Bonden zum einen sehr hohe Anforderungen an die Oberflächenplanarität und -reinheit, und zum anderen sollten die Bondpartner frei von Oxiden sein. Oxidiertes Cu erfordert erhöhte Bondparameter, um die Oxidschicht zu durchbrechen und zuverlässige Cu-Cu-Verbindungen zu erzielen. Diese Bondbedingungen sind für viele sensible Bauelemente nicht geeignet. Aus diesem Grund sollten alternative Technologien mit einer einfachen Technik zum Schutz von Cu vor Oxidation gefunden werden. In dieser Arbeit werden selbstorganisierte Monolagen (SAMs) für den Cu-Oxidationsschutz und die Verbesserung der Cu-Cu-Thermokompression- (TC) und Ultraschall- (US) Flip-Chip-Bondtechnologien untersucht. Die Experimente werden an Si-Chips mit galvanisch aufgebrachten Cu-Microbumps und Cu-Schichten durchgeführt. Die Arbeit beinhaltet die umfassende Charakterisierung der SAM für den Cu-Schutz, die Bewertung der technologischen Parameter für das TC- und US-Flip-Chip-Bonden sowie die Charakterisierung der Cu-Cu-Bondqualität (Scherfestigkeitstests, Bruchflächen- und Mikrostrukturanalysen). Eine Lagerung bei tiefen Temperaturen (bei ‑18 °C und ‑40 °C) bestätigte die langanhaltende Schutzwirkung der kurzkettigen SAMs für das galvanisch abgeschiedene Cu ohne chemisch-mechanische Politur. Der Einfluss der Tieftemperaturlagerung an Luft und der thermischen SAM-Desorption in einer Inertgasatmosphäre auf die TC-Verbindungsqualität wird im Detail analysiert. Die Idee, mit Hilfe der US-Leistung SAM mechanisch zu entfernen und gleichzeitig das US-Flip-Chip-Bonden zu starten, wurde in der Literatur bisher nicht systematisch untersucht. Die Methode ermöglicht kurze Bondzeiten, niedrige Bondtemperaturen und das Bonden an Umgebungsluft. Sowohl beim TC- als auch beim US-Flip-Chip-Bonden zeigt es sich, dass die Scherfestigkeit bei den Proben mit SAM-Passivierung um ca. 30 % höher ist als bei unbeschichteten Proben. Das Vorhandensein von Si- und Ti-Bruchflächen nach den Scherfestigkeitstests ist für die Proben mit der SAM-Passivierung typisch, was auf eine höhere Festigkeit solcher Verbindungen im Vergleich zu ungeschützten Proben schließen lässt. Die Transmissionselektronenmikroskopie (TEM) zeigt keine SAM-Spuren im zentralen Bereich der Cu-Cu-Grenzfläche nach dem US-Flip-Chip-Bonden. Die Ergebnisse dieser Arbeit zeigen die Verbesserung der Bondqualität durch den Einsatz von SAM zum Schutz des Cu vor Oxidation im Vergleich zum üblicherweise angewandten Cu-Vorätzen. Das gefundene technologische Prozessfenster für das US-Flip-Chip-Bonden an Luft bietet eine hohe Bondqualität bei 90 °C und 150 °C, bei 180 MPa, bei einer Bonddauer von 1 s an. Die in dieser Arbeit gewonnenen Erkenntnisse sind ein wichtiger Beitrag zum Verständnis des SAM-Einflusses auf Chips mit galvanischen Cu-Microbumps, bzw. Cu-Schichten, und zur weiteren Anwendung der Cu-Cu-Fine-Pitch-Bondtechnologie in der Mikroelektronik.Cu-Cu bonding is one of the most promising fine-pitch interconnect technologies with solder elimination for 2.5D and 3D system integration. This bonding technology has been intensively investigated in the last years and is currently in application for miniaturized microelectronics products. However, Cu-Cu bonding has very high demands on the sur-face planarity and purity, and the bonding partners should be oxide-free. Oxidized Cu requires elevated bonding parameters in order to break through the oxide layer and achieve reliable Cu-Cu interconnects. Those bonding conditions are undesirable for many devices (e.g. due to the temperature/pressure sensitivity). Therefore, alternative technologies with a simple technique for Cu protection from oxidation are required. Self-assembled monolayers (SAMs) are proposed for the Cu protection and the improvement of the Cu-Cu thermocompression (TC) and ultrasonic (US) flip-chip bonding technologies in this thesis. The experiments were carried out on Si dies with electroplated Cu microbumps and Cu layers. The thesis comprises the comprehensive characterization of the SAM for Cu protection, evaluation of technological parameters for TC and US flip-chip bonding as well as characterization of the Cu-Cu bonding quality (shear strength tests, fracture surface and microstructure analyses). The storage at low temperatures (at ‑18 °C and ‑40 °C) confirmed the prolonged protective effect of the short-chain SAMs for the electroplated Cu without chemical-mechanical polishing. The influence of the low-temperature storage in air and the thermal SAM desorption in an inert gas atmosphere on the TC bonding quality was analyzed in detail. The approach of using US power to mechanically remove SAM and simultaneously start the US flip-chip bonding has not been systematically investigated before. The method provides the benefit of short bonding time, low bonding temperature and bonding in ambient air. Both the TC and US flip-chip bonding results featured the shear strength that is approximately 30 % higher for the samples with SAM passivation in comparison to the uncoated samples. The presence of Si and Ti fracture surfaces after the shear strength tests is typical for the samples with the SAM passivation, which suggests a higher strength of such interconnects in comparison to the uncoated samples. The transmission electron microscopy (TEM) indicated no SAM traces at the central region of the Cu-Cu bonding interface after the US flip-chip bonding. The results of this thesis show the improvement of the bonding quality caused by the application of SAM for Cu protection from oxidation in comparison to the commonly applied Cu pre-treatments. The found technological process window for the US flip-chip bonding in air offers high bonding quality at 90 °C and 150 °C, at 180 MPa, for the bonding duration of 1 s. The knowledge gained in this thesis is an important contribution to the understanding of the SAM performance on chips with electroplated Cu microbumps/layers and further application of the Cu-Cu fine-pitch bonding technology for microelectronic devices

Heterogeneous Integration on Silicon-Interconnect Fabric using fine-pitch interconnects (≤10 �m)

Today, the ever-growing data-bandwidth demand is pushing the boundaries of the traditional printed circuit board (PCB) based integration schemes. Moreover, with the apparent saturation of semiconductor scaling, commonly called Moore's law, system scaling warrants a paradigm shift in packaging technologies, assembly techniques, and integration methodologies. In this work, a superior alternative to PCBs called the Silicon-Interconnect Fabric (Si-IF) is investigated. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform for wafer-scale systems. In this technology, unpackaged dielets are assembled on the Si-IF at small inter-dielet spacings (≤100 �m) using fine-pitch (≤10 �m) die-to-substrate interconnects. A novel assembly process using a solder-less direct metal-metal (gold-gold and copper-copper) thermal compression bonding was developed. Using this process, sub-10 �m pitch interconnects with a low specific contact resistance of ≤0.7 Ω-�m2 were successfully demonstrated. Because of the tightly packed Si-IF assembly, the communication links between the neighboring dies are short (≤500 �m) with low loss (≤2 dB), comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) at low latency (<30 ps), low energy per bit (≤0.03 pJ/b), and high data-rates (up to 10 Gbps/link), corresponding to an aggregate bandwidth up to 8 Tbps/mm. The benefits of the SuperCHIPS protocol were experimentally demonstrated to provide 5-90X higher data-bandwidth, 8-30X lower latency, and 5-40X lower energy per bit compared to existing integration schemes. This dissertation addresses the assembly technology and communication protocols of the Si-IF technology

Atomic-Scale Insights into Light Emitting Diode

In solid-state lightning, GaN-based vertical LED technology has attracted tremendous attention because its luminous efficacy has surpassed the traditional lightning technologies, even the 2014 Nobel Prize in Physics was awarded for the invention of efficient blue LEDs, which enabled eco-friendly and energy-saving white lighting sources. Despite today’s GaN-based blue VLEDs can produce IQE of 90% and EQE of 70-80%, still there exist a major challenge of efficiency droop. Nonetheless, state-of-the-art material characterization and failure analysis tools are inevitable to address that issue. In this context, although LEDs have been characterized by different microscopy techniques, they are still limited to either its semiconductor or active layer, which mainly contributes towards the IQE. This is also one of the reason that today’s LEDs IQE exceeded above 80% but EQE of 70-80% remains. Therefore, to scrutinize the efficiency droop issue, this work focused on developing a novel strategy to investigate key layers of the LED structure, which play the critical role in enhancing the EQE = IQE x LEE factors. Based on that strategy, wafer bonding, reflection, GaN-Ag interface, MQWs and top-textured layers have been systematically investigated under the powerful advanced microscopy techniques of SEM-based TKD/EDX/EBSD, AC-STEM, AFM, Raman spectroscopy, XRD, and PL. Further, based on these correlative microscopy results, optimization suggestions are given for performance enhancement in the LEDs. The objective of this doctoral research is to perform atomic-scale characterization on the VLED layers/interfaces to scrutinize their surface topography, grain morphology, chemical composition, interfacial diffusion, atomic structure and carrier localization mechanism in quest of efficiency droop and reliability issues. The outcome of this research advances in understanding LED device physics, which will facilitate standardization in its design for better smart optoelectronics products

Nanowires for 3d silicon interconnection – low temperature compliant nanowire-polymer film for z-axis interconnect

Semiconductor chip packaging has evolved from single chip packaging to 3D heterogeneous system integration using multichip stacking in a single module. One of the key challenges in 3D integration is the high density interconnects that need to be formed between the chips with through-silicon-vias (TSVs) and inter-chip interconnects. Anisotropic Conductive Film (ACF) technology is one of the low-temperature, fine-pitch interconnect method, which has been considered as a potential replacement for solder interconnects in line with continuous scaling of the interconnects in the IC industry. However, the conventional ACF materials are facing challenges to accommodate the reduced pad and pitch size due to the micro-size particles and the particle agglomeration issue. A new interconnect material - Nanowire Anisotropic Conductive Film (NW-ACF), composed of high density copper nanowires of ~ 200 nm diameter and 10-30 µm length that are vertically distributed in a polymeric template, is developed in this work to tackle the constrains of the conventional ACFs and serves as an inter-chip interconnect solution for potential three-dimensional (3D) applications

Etudes des procédés d'encapsulation hermétique au niveau du substrat par la technologie de transfert de films

Les micro-dispositifs comportant des structures libérées et mobiles sont d une part très sensibles aux variations de leur environnement de travail, et d autre part très fragiles mécaniquement. L étape de découpe du substrat en plusieurs puces est extrêmement agressive et peut entrainer la destruction totale des micro-dispositifs. L encapsulation avant la découpe va alors prémunir les micro-composants lors de cette étape critique et continuer à garantir leur bon fonctionnement tout au long de leur utilisation en conservant la stabilité et la fiabilité de leur performance. Le conditionnement doit en outre interfacer les micro-dispositifs encapsulés avec le monde macroscopique en vue de leur utilisation. De nombreux procédés de fabrication ont déjà été développés pour l élaboration d un conditionnement. C est le cas de l encapsulation puce par puce, substrat - substrat, par couche sacrificielle par exemple. Ils sont toutefois très contraignants (encombrement, compatibilité, coût, ). Nous avons étudié, au cours de cette thèse, un procédé innovant de conditionnement hermétique par transfert de film utilisant une couche à adhésion contrôlée. Cette technologie consiste à élaborer des capots protecteurs sur le substrat moule puis à les reporter collectivement pour encapsuler les micro-dispositifs. Ce procédé est totalement compatible avec un interfaçage électrique de composant qui traverse les cordons de scellement ou le capot. Ce procédé nécessite la maîtrise de la croissance de divers films (C, CxFy, Ni, AlN, parylène, BCB, Au-In) et permet d obtenir des boitiers étanches, hermétiques et robustes qui devraient très rapidement pouvoir être utilisés pour le conditionnement de MEMS.Micro-devices which are composed of free standing or mobile structures are very sensitive to the working condition and mechanically very fragile. The saw dicing steps is very aggressive and it can destroy the micro-devices. Packaging will prevent the micro devices from any damage during this critical step and also take care of it all along its life by controlling its performance stability and reliability. Moreover, the suited devices use needs a connection to the macroscopic word through the packaging. Many packaging process flow has already developed such as pick and place, wafer to wafer, thin film packaging with a sacrificial layer. Nevertheless, they have got many drawbacks (footprint, process compatibility, cost ). We have developed an attractive wafer level hermetic packaging process by film transfer technology during this these. It relies on a transferred molded film cap from a carrier wafer to the donor wafer. Electrical path can be done through the cap or the bonding ring. Cap manufacturing need a high layer growth skill for example in C, CxFy, Ni, AlN, parylène, BCB, Au-In films to make robust, hermetic encapsulation which should be soon used for MEMS packaging.PARIS11-SCD-Bib. électronique (914719901) / SudocSudocFranceF