Book Review

A Scholarly Review of “Error Control for Network-On-Chip Links” (Authors: Bo Fu and Paul Ampadu, 2012)Fu, B.; and Ampadu, P. 2012. Error Control for Network-On-Chip Links.Springer Science+Business Media, LLC, New York, NY, USA.Available: <http://dx.doi.org/10.1007/978-1-4419-9313-7>

Codes for Limited Magnitude Error Correction in Multilevel Cell Memories

Multilevel cell (MLC) memories have been advocated for increasing density at low cost in next generation memories. However, the feature of several bits in a cell reduces the distance between levels; this reduced margin makes such memories more vulnerable to defective phenomena and parameter variations, leading to an error in stored data. These errors typically are of limited magnitude, because the induced change causes the stored value to exceed only a few of the level boundaries. To protect these memories from such errors and ensure that the stored data is not corrupted, Error Correction Codes (ECCs) are commonly used. However, most existing codes have been designed to protect memories in which each cell stores a bit and thus, they are not efficient to protect MLC memories. In this paper, an efficient scheme that can correct up to magnitude-3 errors is presented and evaluated. The scheme is based by combining ECCs that are commonly used to protect traditional memories. In particular, Interleaved Parity (IP) bits and Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes are utilized; both these codes are combined in the proposed IP-DAEC scheme to efficiently provide a strong coding function for correction, thus exceeding the capabilities of most existing coding schemes for limited magnitude errors. The SEC-DAEC code is used to detect the cell in error and correct some bits, while the IP bits identify the remaining erroneous bits in the memory cell. The use of these simple codes results in an efficient implementation of the decoder compared to existing techniques as shown by the evaluation results presented in this paper. The proposed scheme is also competitive in terms of number of parity check bits and memory redundancy. Therefore, the proposed IP-DAEC scheme is a very efficient alternative to protect and correct MLC memories from limited magnitude errors.Pedro Reviriego was partially supported by the TEXEO project (TEC2016-80339-R) funded by the Spanish Research Plan and by the Madrid Community research project TAPIR-CM grant no. P2018/TCS-4496

Statistical mechanics of error exponents for error-correcting codes

Error exponents characterize the exponential decay, when increasing message length, of the probability of error of many error-correcting codes. To tackle the long standing problem of computing them exactly, we introduce a general, thermodynamic, formalism that we illustrate with maximum-likelihood decoding of low-density parity-check (LDPC) codes on the binary erasure channel (BEC) and the binary symmetric channel (BSC). In this formalism, we apply the cavity method for large deviations to derive expressions for both the average and typical error exponents, which differ by the procedure used to select the codes from specified ensembles. When decreasing the noise intensity, we find that two phase transitions take place, at two different levels: a glass to ferromagnetic transition in the space of codewords, and a paramagnetic to glass transition in the space of codes.Comment: 32 pages, 13 figure

VLSI Implementation of Multi-Bit Error Detection and Correction Codes for Space Communications

Data transmission in advanced space communications are suffering with the different types of noises. Further, these noises causeburst errors indata. Thus, the error correction codes (ECC) plays the major role to detect and correct the errors. However, the conventional hamming encoders, decoderswere detected and corrected only one bit error. Therefore, this work implementation the Multi-Bit Error Detection and CorrectionCodes (MBE-DCC) for multiple bits error detection and correction. Initially, MBE-DCC encoding operation is implemented by using generator matrix, which contains both identity bits and parity bits. Then, encoded code word is transmitted into the channel of space communication, where encoded data corrupted by different types of noises, errors. Therefore, the MBE-DCC decoding operation performed at receiver side of space communications, which corrected all the errors using syndrome detection, error location detection, and error correction modules.  The simulations revealed that the proposed MBE-DCC resulted in superior performance than conventional ECC method

An Opportunistic Error Correction Layer for OFDM Systems

In this paper, we propose a novel cross layer scheme to lower power\ud consumption of ADCs in OFDM systems, which is based on resolution\ud adaptive ADCs and Fountain codes. The key part in the new proposed\ud system is that the dynamic range of ADCs can be reduced by\ud discarding the packets which are transmitted over 'bad' sub\ud carriers. Correspondingly, the power consumption in ADCs can be\ud reduced. Also, the new system does not process all the packets but\ud only processes surviving packets. This new error correction layer\ud does not require perfect channel knowledge, so it can be used in a\ud realistic system where the channel is estimated. With this new\ud approach, more than 70% of the energy consumption in the ADC can be\ud saved compared with the conventional IEEE 802.11a WLAN system under\ud the same channel conditions and throughput. The ADC in a receiver\ud can consume up to 50% of the total baseband energy. Moreover, to\ud reduce the overhead of Fountain codes, we apply message passing and\ud Gaussian elimination in the decoder. In this way, the overhead is\ud 3% for a small block size (i.e. 500 packets). Using both methods\ud results in an efficient system with low delay

2D Parity Product Code for TSV online fault correction and detection

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs).  However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults.  In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code.  In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction