Design and Implementation of Belief Propagation Symbol Detectors for Wireless Intersymbol Interference Channels

In modern wireless communication systems, intersymbol interference (ISI) introduced by frequency selective fading is one of the major impairments to reliable data communication. In ISI channels, the receiver observes the superposition of multiple delayed reflections of the transmitted signal, which will result errors in the decision device. As the data rate increases, the effect of ISI becomes severe. To combat ISI, equalization is usually required for symbol detectors. The optimal maximum-likelihood sequence estimation (MLSE) based on the Viterbi algorithm (VA) may be used to estimate the transmitted sequence in the presence of the ISI. However, the computational complexity of the MLSE increases exponentially with the length of the channel impulse response (CIR). Even in channels which do not exhibit significant time dispersion, the length of the CIR will effectively increase as the sampling rate goes higher. Thus the optimal MLSE is impractical to implement in the majority of practical wireless applications. This dissertation is devoted to exploring practically implementable symbol detectors with near-optimal performance in wireless ISI channels. Particularly, we focus on the design and implementation of an iterative detector based on the belief propagation (BP) algorithm. The advantage of the BP detector is that its complexity is solely dependent on the number of nonzero coefficients in the CIR, instead of the length of the CIR. We also extend the work of BP detector design for various wireless applications. Firstly, we present a partial response BP (PRBP) symbol detector with near-optimal performance for channels which have long spanning durations but sparse multipath structure. We implement the architecture by cascading an adaptive linear equalizer (LE) with a BP detector. The channel is first partially equalized by the LE to a target impulse response (TIR) with only a few nonzero coefficients remaining. The residual ISI is then canceled by a more sophisticated BP detector. With the cascaded LE-BP structure, the symbol detector is capable to achieve a near-optimal error rate performance with acceptable implementation complexity. Moreover, we present a pipeline high-throughput implementation of the detector for channel length 30 with quadrature phase-shift keying (QPSK) modulation. The detector can achieve a maximum throughput of 206 Mb/s with an estimated core area of 3.162 mm^{2} using 90-nm technology node. At a target frequency of 515 MHz, the dynamic power is about 1.096 W. Secondly, we investigate the performance of aforementioned PRBP detector under a more generic 3G channel rather than the sparse channel. Another suboptimal partial response maximum-likelihood (PRML) detector is considered for comparison. Similar to the PRBP detector, the PRML detector also employs a hybrid two-stage scheme, in order to allow a tradeoff between performance and complexity. In simulations, we consider a slow fading environment and use the ITU-R 3G channel models. From the numerical results, it is shown that in frequency-selective fading wireless channels, the PRBP detector provides superior performance over both the traditional minimum mean squared error linear equalizer (MMSE-LE) and the PRML detector. Due to the effect of colored noise, the PRML detector in fading wireless channels is not as effective as it is in magnetic recording applications. Thirdly, we extend our work to accommodate the application of Advanced Television Systems Committee (ATSC) digital television (DTV) systems. In order to reduce error propagation caused by the traditional decision feedback equalizer (DFE) in DTV receiver, we present an adaptive decision feedback sparsening filter BP (DFSF-BP) detector, which is another form of PRBP detector. Different from the aforementioned LE-BP structure, in the DFSF-BP scheme, the BP detector is followed by a nonlinear filter called DFSF as the partial response equalizer. In the first stage, the DFSF employs a modified feedback filter which leaves the strongest post-cursor ISI taps uncorrected. As a result, a long ISI channel is equalized to a sparse channel having only a small number of nonzero taps. In the second stage, the BP detector is applied to mitigate the residual ISI. Since the channel is typically time-varying and suffers from Doppler fading, the DFSF is adapted using the least mean square (LMS) algorithm, such that the amplitude and the locations of the nonzero taps of the equalized sparse channel appear to be fixed. As such, the channel appears to be static during the second stage of equalization which consists of the BP detector. Simulation results demonstrate that the proposed scheme outperforms the traditional DFE in symbol error rate, under both static channels and dynamic ATSC channels. Finally, we study the symbol detector design for cooperative communications, which have attracted a lot of attention recently for its ability to exploit increased spatial diversity available at distributed antennas on other nodes. A system framework employing non-orthogonal amplify-and-forward half-duplex relays through ISI channels is developed. Based on the system model, we first design and implement an optimal maximum-likelihood detector based on the Viterbi algorithm. As the relay period increases, the effective CIR between the source and the destination becomes long and sparse, which makes the optimal detector impractical to implement. In order to achieve a balance between the computational complexity and performance, several sub-optimal detectors are proposed. We first present a multitrellis Viterbi algorithm (MVA) based detector which decomposes the original trellis into multiple parallel irregular sub-trellises by investigating the dependencies between the received symbols. Although MVA provides near-optimal performance, it is not straightforward to decompose the trellis for arbitrary ISI channels. Next, the decision feedback sequence estimation (DFSE) based detector and BP-based detector are proposed for cooperative ISI channels. Traditionally these two detectors are used with fixed, static channels. In our model, however, the effective channel is periodically time-varying, even when the component channels themselves are static. Consequently, we modify these two detector to account for cooperative ISI channels. Through simulations in frequency selective fading channels, we demonstrate the uncoded performance of the DFSE detector and the BP detector when compared to the optimal MLSE detector. In addition to quantifying the performance of these detectors, we also include an analysis of the implementation complexity as well as a discussion on complexity/performance tradeoffs

A DAC and comparator for a 100MHz decision feedback equalization loop

Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW

Front-end receiver for miniaturised ultrasound imaging

Point of care ultrasonography has been the focus of extensive research over the past few decades. Miniaturised, wireless systems have been envisaged for new application areas, such as capsule endoscopy, implantable ultrasound and wearable ultrasound. The hardware constraints of such small-scale systems are severe, and tradeoffs between power consumption, size, data bandwidth and cost must be carefully balanced. To address these challenges, two synthetic aperture receiver architectures are proposed and compared. The architectures target highly miniaturised, low cost, B-mode ultrasound imaging systems. The first architecture utilises quadrature (I/Q) sampling to minimise the signal bandwidth and computational load. Synthetic aperture beamforming is carried out using a single-channel, pipelined protocol in order to minimise system complexity and power consumption. A digital beamformer dynamically apodises and focuses the data by interpolating and applying complex phase rotations to the I/Q samples. The beamformer is implemented on a Spartan-6 FPGA and consumes 296mW for a frame rate of 7Hz. The second architecture employs compressive sensing within the finite rate of innovation (FRI) framework to further reduce the data bandwidth. Signals are sampled below the Nyquist frequency, and then transmitted to a digital back-end processor, which reconstructs I/Q components non-linearly, and then carries out synthetic aperture beamforming. Both architectures were tested in hardware using a single-channel analogue front-end (AFE) that was designed and fabricated in AMS 0.35μm CMOS. The AFE demodulates RF ultrasound signals sequentially into I/Q components, and comprises a low-noise preamplifier, mixer, programmable gain amplifier (PGA) and lowpass filter. A variable gain low noise preamplifier topology is used to enable quasi-exponential time-gain control (TGC). The PGA enables digital selection of three gain values (15dB, 22dB and 25.5dB). The bandwidth of the lowpass filter is also selectable between 1.85MHz, 510kHz and 195kHz to allow for testing of both architectural frameworks. The entire AFE consumes 7.8 mW and occupies an area of 1.5×1.5 mm. In addition to the AFE, this thesis also presents the design of a pseudodifferential, log-domain multiplier-filter or “multer” which demodulates low-RF signals in the current-domain. This circuit targets high impedance transducers such as capacitive micromachined ultrasound transducers (CMUTs) and offers a 20dB improvement in dynamic range over the voltage-mode AFE. The bandwidth is also electronically tunable. The circuit was implemented in 0.35μm BiCMOS and was simulated in Cadence; however, no fabrication results were obtained for this circuit. B-mode images were obtained for both architectures. The quadrature SAB method yields a higher image SNR and 9% lower root mean squared error with respect to the RF-beamformed reference image than the compressive SAB method. Thus, while both architectures achieve a significant reduction in sampling rate, system complexity and area, the quadrature SAB method achieves better image quality. Future work may involve the addition of multiple receiver channels and the development of an integrated system-on-chip.Open Acces

Advances in Modeling and Signal Processing for Bit-Patterned Magnetic Recording Channels with Written-In Errors

In the past perpendicular magnetic recording on continuous media has served as the storage mechanism for the hard-disk drive (HDD) industry, allowing for growth in areal densities approaching 0.5 Tb/in2. Under the current system design, further increases are limited by the superparamagnetic effect where the medium's thermal energy destabilizes the individual bit domains used for storage. In order to provide for future growth in the area of magnetic recording for disk drives, a number of various technology shifts have been proposed and are currently undergoing considerable research. One promising option involves switching to a discrete medium in the form of individual bit islands, termed bit-patterned magnetic recording (BPMR).When switching from a continuous to a discrete media, the problems encountered become substantial for every aspect of the hard-disk drive design. In this dissertation the complications in modeling and signal processing for bit-patterned magnetic recording are investigated where the write and read processes along with the channel characteristics present considerable challenges. For a target areal density of 4 Tb/in2, the storage process is hindered by media noise, two-dimensional (2D) intersymbol interference (ISI), electronics noise and written-in errors introduced during the write process. Thus there is a strong possibility that BPMR may prove intractable as a future HDD technology at high areal densities because the combined negative effects of the many error sources produces an environment where current signal processing techniques cannot accurately recover the stored data. The purpose here is to exploit advanced methods of detection and error correction to show that data can be effectively recovered from a BPMR channel in the presence of multiple error sources at high areal densities.First a practical model for the readback response of an individual island is established that is capable of representing its 2D nature with a Gaussian pulse. Various characteristics of the readback pulse are shown to emerge as it is subjected to the degradation of 2D media noise. The writing of the bits within a track is also investigated with an emphasis on the write process's ability to inject written-in errors in the data stream resulting from both a loss of synchronization of the write clock and the interaction of the local-scale magnetic fields under the influence of the applied write field.To facilitate data recovery in the presence of BPMR's major degradations, various detection and error-correction methods are utilized. For single-track equalization of the channel output, noise prediction is incorporated to assist detection with increased levels of media noise. With large detrimental amounts of 2D ISI and media noise present in the channel at high areal densities, a 2D approach known as multi-track detection is investigated where multiple tracks are sensed by the read heads and then used to extract information on the target track. For BPMR the output of the detector still possesses the uncorrected written-in errors. Powerful error-correction codes based on finite geometries are employed to help recover the original data stream. Increased error-correction is sought by utilizing two-fold EG codes in combination with a form of automorphism decoding known as auto-diversity. Modifications to the parity-check matrices of the error-correction codes are also investigated for the purpose of attempting more practical applications of the decoding algorithms based on belief propagation. Under the proposed techniques it is shown that effective data recovery is possible at an areal density of 4 Tb/in2 in the presence of all significant error sources except for insertions and deletions. Data recovery from the BPMR channel with insertions and deletions remains an open problem

Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters

A general framework for performance optimization of continuous-time OTA-C (Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary order are developed based on the matrix description of a general OTA-C filter model . Since these procedures use OTA macromodels, they can be used to obtain the results significantly faster than transistor-level simulation. In the case of transient analysis, the speed-up may be as much as three orders of magnitude without almost no loss of accuracy. This makes it possible to carry out direct numerical optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. The above features are a basis to build automated optimization procedures for OTA-C filters. In particular, a systematic optimization procedure using equivalence transformations is proposed. The research also proposes suitable software implementations of the optimization process. The first part of the research proposes a general performance optimization procedure and to verify the process two application type examples are mentioned. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in standard 0.5mm CMOS process. The second part of the research proposes a new linearization technique to improve the linearity of an OTA using an Active Error Feedforward technique. Most present day applications require very high linear circuits combined with low noise and low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm CMOS process. The measurement results for the filter and the stand alone OTA have been discussed. The research focuses on these issues