Protein folding on the ribosome studied using NMR spectroscopy

NMR spectroscopy is a powerful tool for the investigation of protein folding and misfolding, providing a characterization of molecular structure, dynamics and exchange processes, across a very wide range of timescales and with near atomic resolution. In recent years NMR methods have also been developed to study protein folding as it might occur within the cell, in a de novo manner, by observing the folding of nascent polypeptides in the process of emerging from the ribosome during synthesis. Despite the 2.3 MDa molecular weight of the bacterial 70S ribosome, many nascent polypeptides, and some ribosomal proteins, have sufficient local flexibility that sharp resonances may be observed in solution-state NMR spectra. In providing information on dynamic regions of the structure, NMR spectroscopy is therefore highly complementary to alternative methods such as X-ray crystallography and cryo-electron microscopy, which have successfully characterized the rigid core of the ribosome particle. However, the low working concentrations and limited sample stability associated with ribosome-nascent chain complexes means that such studies still present significant technical challenges to the NMR spectroscopist. This review will discuss the progress that has been made in this area, surveying all NMR studies that have been published to date, and with a particular focus on strategies for improving experimental sensitivity

Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

JaxNet: Scalable Blockchain Network

Today's world is organized based on merit and value. A single global currency that's decentralized is needed for a global economy. Bitcoin is a partial solution to this need, however it suffers from scalability problems which prevent it from being mass-adopted. Also, the deflationary nature of bitcoin motivates people to hoard and speculate on them instead of using them for day to day transactions. We propose a scalable, decentralized cryptocurrency that is based on Proof of Work.The solution involves having parallel chains in a closed network using a mechanism which rewards miners proportional to their effort in maintaining the network.The proposed design introduces a novel approach for solving scalability problem in blockchain network based on merged mining.Comment: 55 pages. 10 figure

Visual analytics for supply network management: system design and evaluation

We propose a visual analytic system to augment and enhance decision-making processes of supply chain managers. Several design requirements drive the development of our integrated architecture and lead to three primary capabilities of our system prototype. First, a visual analytic system must integrate various relevant views and perspectives that highlight different structural aspects of a supply network. Second, the system must deliver required information on-demand and update the visual representation via user-initiated interactions. Third, the system must provide both descriptive and predictive analytic functions for managers to gain contingency intelligence. Based on these capabilities we implement an interactive web-based visual analytic system. Our system enables managers to interactively apply visual encodings based on different node and edge attributes to facilitate mental map matching between abstract attributes and visual elements. Grounded in cognitive fit theory, we demonstrate that an interactive visual system that dynamically adjusts visual representations to the decision environment can significantly enhance decision-making processes in a supply network setting. We conduct multi-stage evaluation sessions with prototypical users that collectively confirm the value of our system. Our results indicate a positive reaction to our system. We conclude with implications and future research opportunities.The authors would like to thank the participants of the 2015 Businessvis Workshop at IEEE VIS, Prof. Benoit Montreuil, and Dr. Driss Hakimi for their valuable feedback on an earlier version of the software; Prof. Manpreet Hora for assisting with and Georgia Tech graduate students for participating in the evaluation sessions; and the two anonymous reviewers for their detailed comments and suggestions. The study was in part supported by the Tennenbaum Institute at Georgia Tech Award # K9305. (K9305 - Tennenbaum Institute at Georgia Tech Award)Accepted manuscrip

Anyonic entanglement renormalization

We introduce a family of variational ansatz states for chains of anyons which optimally exploits the structure of the anyonic Hilbert space. This ansatz is the natural analog of the multi-scale entanglement renormalization ansatz for spin chains. In particular, it has the same interpretation as a coarse-graining procedure and is expected to accurately describe critical systems with algebraically decaying correlations. We numerically investigate the validity of this ansatz using the anyonic golden chain and its relatives as a testbed. This demonstrates the power of entanglement renormalization in a setting with non-abelian exchange statistics, extending previous work on qudits, bosons and fermions in two dimensions.Comment: 19 pages, 10 figures, v2: extended, updated to match published versio

Quantum Communication through Spin Chain Dynamics: an Introductory Overview

We present an introductory overview of the use of spin chains as quantum wires, which has recently developed into a topic of lively interest. The principal motivation is in connecting quantum registers without resorting to optics. A spin chain is a permanently coupled 1D system of spins. When one places a quantum state on one end of it, the state will be dynamically transmitted to the other end with some efficiency if the spins are coupled by an exchange interaction. No external modulations or measurements on the body of the chain, except perhaps at the very ends, is required for this purpose. For the simplest (uniformly coupled) chain and the simplest encoding (single qubit encoding), however, dispersion reduces the quality of transfer. We present a variety of alternatives proposed by various groups to achieve perfect quantum state transfer through spin chains. We conclude with a brief discussion of the various directions in which the topic is developing.Comment: Material covered till Dec 200

Asynchronous techniques for system-on-chip design

SoC design will require asynchronous techniques as the large parameter variations across the chip will make it impossible to control delays in clock networks and other global signals efficiently. Initially, SoCs will be globally asynchronous and locally synchronous (GALS). But the complexity of the numerous asynchronous/synchronous interfaces required in a GALS will eventually lead to entirely asynchronous solutions. This paper introduces the main design principles, methods, and building blocks for asynchronous VLSI systems, with an emphasis on communication and synchronization. Asynchronous circuits with the only delay assumption of isochronic forks are called quasi-delay-insensitive (QDI). QDI is used in the paper as the basis for asynchronous logic. The paper discusses asynchronous handshake protocols for communication and the notion of validity/neutrality tests, and completion tree. Basic building blocks for sequencing, storage, function evaluation, and buses are described, and two alternative methods for the implementation of an arbitrary computation are explained. Issues of arbitration, and synchronization play an important role in complex distributed systems and especially in GALS. The two main asynchronous/synchronous interfaces needed in GALS-one based on synchronizer, the other on stoppable clock-are described and analyzed

Network-on-Chip

Addresses the Challenges Associated with System-on-Chip Integration Network-on-Chip: The Next Generation of System-on-Chip Integration examines the current issues restricting chip-on-chip communication efficiency, and explores Network-on-chip (NoC), a promising alternative that equips designers with the capability to produce a scalable, reusable, and high-performance communication backbone by allowing for the integration of a large number of cores on a single system-on-chip (SoC). This book provides a basic overview of topics associated with NoC-based design: communication infrastructure design, communication methodology, evaluation framework, and mapping of applications onto NoC. It details the design and evaluation of different proposed NoC structures, low-power techniques, signal integrity and reliability issues, application mapping, testing, and future trends. Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design. This text comprises 12 chapters and covers: The evolution of NoC from SoC—its research and developmental challenges NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces The router design strategies followed in NoCs The evaluation mechanism of NoC architectures The application mapping strategies followed in NoCs Low-power design techniques specifically followed in NoCs The signal integrity and reliability issues of NoC The details of NoC testing strategies reported so far The problem of synthesizing application-specific NoCs Reconfigurable NoC design issues Direction of future research and development in the field of NoC Network-on-Chip: The Next Generation of System-on-Chip Integration covers the basic topics, technology, and future trends relevant to NoC-based design, and can be used by engineers, students, and researchers and other industry professionals interested in computer architecture, embedded systems, and parallel/distributed systems