5,074 research outputs found
Radiation safety based on the sky shine effect in reactor
In the reactor operation, neutrons and gamma rays are the most dominant radiation.
As protection, lead and concrete shields are built around the reactor. However, the radiation
can penetrate the water shielding inside the reactor pool. This incident leads to the occurrence
of sky shine where a physical phenomenon of nuclear radiation sources was transmitted
panoramic that extends to the environment. The effect of this phenomenon is caused by the
fallout radiation into the surrounding area which causes the radiation dose to increase. High
doses of exposure cause a person to have stochastic effects or deterministic effects. Therefore,
this study was conducted to measure the radiation dose from sky shine effect that scattered
around the reactor at different distances and different height above the reactor platform. In this
paper, the analysis of the radiation dose of sky shine effect was measured using the
experimental metho
Channel Characterization for Chip-scale Wireless Communications within Computing Packages
Wireless Network-on-Chip (WNoC) appears as a promising alternative to
conventional interconnect fabrics for chip-scale communications. WNoC takes
advantage of an overlaid network composed by a set of millimeter-wave antennas
to reduce latency and increase throughput in the communication between cores.
Similarly, wireless inter-chip communication has been also proposed to improve
the information transfer between processors, memory, and accelerators in
multi-chip settings. However, the wireless channel remains largely unknown in
both scenarios, especially in the presence of realistic chip packages. This
work addresses the issue by accurately modeling flip-chip packages and
investigating the propagation both its interior and its surroundings. Through
parametric studies, package configurations that minimize path loss are obtained
and the trade-offs observed when applying such optimizations are discussed.
Single-chip and multi-chip architectures are compared in terms of the path loss
exponent, confirming that the amount of bulk silicon found in the pathway
between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on
Networks-on-Chip (NOCS 2018); Torino, Italy; October 201
CMOS Vision Sensors: Embedding Computer Vision at Imaging Front-Ends
CMOS Image Sensors (CIS) are key for imaging technol-ogies. These chips are conceived for capturing opticalscenes focused on their surface, and for delivering elec-trical images, commonly in digital format. CISs may incor-porate intelligence; however, their smartness basicallyconcerns calibration, error correction and other similartasks. The term CVISs (CMOS VIsion Sensors) definesother class of sensor front-ends which are aimed at per-forming vision tasks right at the focal plane. They havebeen running under names such as computational imagesensors, vision sensors and silicon retinas, among others. CVIS and CISs are similar regarding physical imple-mentation. However, while inputs of both CIS and CVISare images captured by photo-sensors placed at thefocal-plane, CVISs primary outputs may not be imagesbut either image features or even decisions based on thespatial-temporal analysis of the scenes. We may hencestate that CVISs are more âintelligentâ than CISs as theyfocus on information instead of on raw data. Actually,CVIS architectures capable of extracting and interpretingthe information contained in images, and prompting reac-tion commands thereof, have been explored for years inacademia, and industrial applications are recently ramp-ing up.One of the challenges of CVISs architects is incorporat-ing computer vision concepts into the design flow. Theendeavor is ambitious because imaging and computervision communities are rather disjoint groups talking dif-ferent languages. The Cellular Nonlinear Network Univer-sal Machine (CNNUM) paradigm, proposed by Profs.Chua and Roska, defined an adequate framework forsuch conciliation as it is particularly well suited for hard-ware-software co-design [1]-[4]. This paper overviewsCVISs chips that were conceived and prototyped at IMSEVision Lab over the past twenty years. Some of them fitthe CNNUM paradigm while others are tangential to it. Allthem employ per-pixel mixed-signal processing circuitryto achieve sensor-processing concurrency in the quest offast operation with reduced energy budget.Junta de AndalucĂa TIC 2012-2338Ministerio de EconomĂa y Competitividad TEC 2015-66878-C3-1-R y TEC 2015-66878-C3-3-
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