Multi-criteria optimization for energy-efficient multi-core systems-on-chip

The steady down-scaling of transistor dimensions has made possible the evolutionary progress leading to today’s high-performance multi-GHz microprocessors and core based System-on-Chip (SoC) that offer superior performance, dramatically reduced cost per function, and much-reduced physical size compared to their predecessors. On the negative side, this rapid scaling however also translates to high power densities, higher operating temperatures and reduced reliability making it imperative to address design issues that have cropped up in its wake. In particular, the aggressive physical miniaturization have increased CMOS fault sensitivity to the extent that many reliability constraints pose threat to the device normal operation and accelerate the onset of wearout-based failures. Among various wearout-based failure mechanisms, Negative biased temperature instability (NBTI) has been recognized as the most critical source of device aging. The urge of reliable, low-power circuits is driving the EDA community to develop new design techniques, circuit solutions, algorithms, and software, that can address these critical issues. Unfortunately, this challenge is complicated by the fact that power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on compact architectures, scaled supply voltages, and small devices. This dissertation focuses on methodologies to bridge this gap and establishes an important link between low-power solutions and aging effects. More specifically, we proposed new architectural solutions based on power management strategies to enable the design of low-power, aging aware cache memories. Cache memories are one of the most critical components for warranting reliable and timely operation. However, they are also more susceptible to aging effects. Due to symmetric structure of a memory cell, aging occurs regardless of the fact that a cell (or word) is accessed or not. Moreover, aging is a worst-case matric and line with worst-case access pattern determines the aging of the entire cache. In order to stop the aging of a memory cell, it must be put into a proper idle state when a cell (or word) is not accessed which require proper management of the idleness of each atomic unit of power management. We have proposed several reliability management techniques based on the idea of cache partitioning to alleviate NBTI-induced aging and obtain joint energy and lifetime benefits. We introduce graceful degradation mechanism which allows different cache blocks into which a cache is partitioned to age at different rates. This implies that various sub-blocks become unreliable at different times, and the cache keeps functioning with reduced efficiency. We extended the capabilities of this architecture by integrating the concept of reconfigurable caches to maintain the performance of the cache throughout its lifetime. By this strategy, whenever a block becomes unreliable, the remaining cache is reconfigured to work as a smaller size cache with only a marginal degradation of performance. Many mission-critical applications require guaranteed lifetime of their operations and therefore the hardware implementing their functionality. Such constraints are usually enforced by means of various reliability enhancing solutions mostly based on redundancy which are not energy-friendly. In our work, we have proposed a novel cache architecture in which a smart use of cache partitions for redundancy allows us to obtain cache that meet a desired lifetime target with minimal energy consumption

Application of a simplified thermal-electric model of a sodium-nickel chloride battery energy storage system to a real case residential prosumer

Recently, power system customers have changed the way they interact with public networks, playing a more and more active role. End-users first installed local small-size generating units, and now they are being equipped with storage devices to increase the self-consumption rate. By suitably managing local resources, the provision of ancillary services and aggregations among several end-users are expected evolutions in the near future. In the upcoming market of household-sized storage devices, sodium-nickel chloride technology seems to be an interesting alternative to lead-acid and lithium-ion batteries. To accurately investigate the operation of the NaNiCl2 battery system at the residential level, a suitable thermoelectric model has been developed by the authors, starting from the results of laboratory tests. The behavior of the battery internal temperature has been characterized. Then, the designed model has been used to evaluate the economic profitability in installing a storage system in the case that end-users are already equipped with a photovoltaic unit. To obtain realistic results, real field measurements of customer consumption and solar radiation have been considered. A concrete interest in adopting the sodium-nickel chloride technology at the residential level is confirmed, taking into account the achievable benefits in terms of economic income, back-up supply, and increased indifference to the evolution of the electricity market

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Implementing a hybrid series bus with gas turbine device - a preliminary study

This paper presents the implementation of an hybrid series Bus with a gas turbine, as thermal engine. The hybridization methodology for transforming city buses, substituting the original gasoline/diesel engine with a micro gas turbine device (intended as range extender), into a series hybrid vehicle has investigated and its feasibility analyzed. The study was conducted by the university of Rome “Sapienza” in collaboration with several enterprises. The idea is to design a hybrid power train that can be installed in a typical city bus, which means that all systems and components will be influenced by the limited space available. In this paper the details of the mechanical and electrical realization of the power train will be discussed. The hybrid system also includes consideration on the battery pack and the vehicle management logic. The proposed solution obtains a reduction in fuel consumption higher than 20%, in comparison with normal commercial fleet