A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s

This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115--225 μm2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 μW and achieves an energy efficiency of 4.4 fJ/conversion-step

Design and implementation of a wideband sigma delta ADC

Abstract. High-speed and wideband ADCs have become increasingly important in response to the growing demand for high-speed wireless communication services. Continuous time sigma delta modulators (CTƩ∆M), well-known for their oversampling and noise shaping properties, offer a promising solution for low-power and high-speed design in wireless applications. The objective of this thesis is to design and implement a wideband CTƩ∆M for a global navigation satellite system(GNSS) receiver. The targeted modulator architecture is a 3rdorder single-bit CTƩ∆M, specifically designed to operate within a 15 MHz signal bandwidth. With an oversampling ratio of 25, the ADC’s sampling frequency is set at 768 MHz. The design goal is to achieve a theoretical signal to noise ratio (SNR) of 55 dB. This thesis focuses on the design and implementation of the CTƩ∆M, building upon the principles of a discrete time Ʃ∆ modulator, and leveraging system-level simulation and formulations. A detailed explanation of the coefficient calculation procedure specific to CTƩ∆ modulators is provided, along with a "top-down" design approach that ensures the specified requirements are met. MATLAB scripts for coefficient calculation are also included. To overcome the challenges associated with the implementation of CTƩ∆ modulators, particularly excess loop delay and clock jitter sensitivity, this thesis explores two key strategies: the introduction of a delay compensation path and the utilization of a finite impulse response (FIR) feedback DAC. By incorporating a delay compensation path, the stability of the modulator can be ensured and its noise transfer function (NTF) can be restored. Additionally, the integration of an FIR feedback DAC addresses the issue of clock jitter sensitivity, enhancing the overall performance and robustness of the CTƩ∆M. The CTƩ∆Ms employ the cascade of integrators with feed forward (CIFF) and cascade of integrators with feedforward and feedback (CIFF-B) topologies, with a particular emphasis on the CIFF-B configuration using 22nm CMOS technology node and a supply voltage of 0.8 V. Various simulations are performed to validate the modulator’s performance. The simulation results demonstrate an achievable SNR of 55 dB with a power consumption of 1.36 mW. Furthermore, the adoption of NTF zero optimization techniques enhances the SNR to 62 dB.Laajakaistaisen jatkuva-aikaisen sigma delta-AD-muuntimen suunnittelu ja toteutus. Tiivistelmä. Nopeat ja laajakaistaiset AD-muuntimet ovat tulleet entistä tärkeämmiksi nopeiden langattomien kommunikaatiopalvelujen kysynnän kasvaessa. Jatkuva-aikaiset sigma delta -modulaattorit (CTƩ∆M), joissa käytetään ylinäytteistystä ja kohinanmuokkausta, tarjoavat lupaavan ratkaisun matalan tehonkulutuksen ja nopeiden langattomien sovellusten suunnitteluun. Tämän työn tarkoituksena on suunnitella ja toteuttaa laajakaistainen jatkuva -aikainen sigma delta -modulaattori satelliittipaikannusjärjestelmien (GNSS) vastaanottimeen. Arkkitehtuuriltaan modulaattori on kolmannen asteen 1-bittinen CTƩ∆M, jolla on 15MHz:n signaalikaistanleveys. Ylinäytteistyssuhde on 25 ja AD muuntimen näytteistystaajuus 768 MHz. Tavoitteena on saavuttaa teoreettinen 55 dB signaalikohinasuhde (SNR). Tämä työ keskittyy jatkuva-aikaisen sigma delta -modulaattorin suunnitteluun ja toteutukseen, perustuen diskreettiaikaisen Ʃ∆-modulaattorin periaatteisiin ja systeemitason simulointiin ja mallitukseen. Jatkuva-aikaisen sigma delta -modulaattorin kertoimien laskentamenetelmä esitetään yksityiskohtaisesti, ja vaatimusten täyttyminen varmistetaan “top-down” -suunnitteluperiaatteella. Liitteenä on kertoimien laskemiseen käytetty MATLAB-koodi. Jatkuva-aikaisten sigma delta -modulaattoreiden erityishaasteiden, liian pitkän silmukkaviiveen ja kellojitterin herkkyyden, voittamiseksi tutkitaan kahta strategiaa, viiveen kompensointipolkua ja FIR takaisinkytkentä -DA muunninta. Viivekompensointipolkua käyttämällä modulaattorin stabiilisuus ja kohinansuodatusfunktio saadaan varmistettua ja korjattua. Lisäksi FIR takaisinkytkentä -DA-muuntimen käyttö pienentää kellojitteriherkkyyttä, parantaen jatkuva aikaisen sigma delta -modulaattorin kokonaissuorituskykyä ja luotettavuutta. Toteutetuissa jatkuva-aikaisissa sigma delta -modulaattoreissa on kytketty peräkkäin integraattoreita myötäkytkentärakenteella (CIFF) ja toisessa sekä myötä- että takaisinkytkentärakenteella (CIFF-B). Päähuomio on CIFF-B rakenteessa, joka toteutetaan 22nm CMOS prosessissa käyttäen 0.8 voltin käyttöjännitettä. Suorityskyky varmistetaan erilaisilla simuloinneilla, joiden perusteella 55 dB SNR saavutetaan 1.36 mW tehonkulutuksella. Lisäksi kohinanmuokkausfunktion optimoinnilla SNR saadaan nostettua 62 desibeliin

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

A CCO-based Sigma-Delta ADC

Analog-to-digital converter (ADC) is one of the most important blocks in nowadays systems. Most of the data processing is done in the digital domain however, the physical world is analog. ADCs make the bridge between analog and digital domain. The constant and unstoppable evolution of the technology makes the dimensions of the transistors smaller and smaller, and the classical solutions of Sigma-Delta converters (ΣΔ) are becoming more challenging to design because they normally require high active gain blocks difficult to achieve in modern technologies. In recent years, the use of voltage-controlled oscillators (VCO) in ΣΔ converters has been widely explored, since they are used as quantizers and their implementations are mostly made with digital blocks, which is preferable with new technologies. In this work a second-order ΣΔ modulator based on two current-controlled oscillators (CCO) with a single output phase and an independent phase generator for each CCO that generates any desired number of phases using the oscillation of its CCO as reference has been proposed. This ΣΔ modulator was studied through a MATLAB/Simulink® model, obtaining promising results with the SNDR in the order of 75 dB, at a sampling frequency of 1 GHz, and a bandwidth of 5 MHz, corresponding to an ENOB of, approximately, 12 bits

Design of a wideband low-power continuous-time sigma-delta (ΣΔ) analog-to-digital converter (ADC) in 90nm CMOS technology

The growing trend in VLSI systems is to shift more signal processing functionality from analog to digital domain to reduce manufacturing cost and improve reliability. It has resulted in the demand for wideband high-resolution analog-to-digital converters (ADCs). There are many different techniques for doing analog-to-digital conversions. Oversampling ADC based on sigma-delta (ΣΔ) modulation is receiving a lot of attention due to its significantly relaxed matching requirements on analog components. Moreover, it does not need a steep roll-off anti-aliasing filter. A ΣΔ ADC can be implemented either as a discrete time system or a continuous time one. Nowadays growing interest is focused on the continuous-time ΣΔ ADC for its use in the wideband and low-power applications, such as medical imaging, portable ultrasound systems, wireless receivers, and test equipments. A continuous-time ΣΔ ADC offers some important advantages over its discrete-time counterpart, including higher sampling frequency, intrinsic anti-alias filtering, much relaxed sampling network requirements, and low-voltage implementation. Especially it has the potential in achieving low power consumption. This dissertation presents a novel fifth-order continuous-time ΣΔ ADC which is implemented in a 90nm CMOS technology with single 1.0-V power supply. To speed up design process, an improved direct design method is proposed and used to design the loop filter transfer function. To maximize the in-band gain provided by the loop filter, thus maximizing in-band noise suppression, the excess loop delay must be kept minimum. In this design, a very low latency 4-bit flash quantizer with digital-to-analog (DAC) trimming is utilized. DAC trimming technique is used to correct the quantizer offset error, which allows minimum-sized transistors to be used for fast and low-power operation. The modulator has sampling clock of 800MHz. It achieves a dynamic range (DR) of 75dB and a signal-to-noise-and-distortion ratio (SNDR) of 70dB over 25MHz input signal bandwidth with 16.4mW power dissipation. Our work is among the most improved published to date. It uses the lowest supply voltage and has the highest input signal bandwidth while dissipating the lowest power among the bandwidths exceeding 15MHz

A CMOS Digital Beamforming Receiver

As the demand for high speed communication is increasing, emerging wireless techniques seek to utilize unoccupied frequency ranges, such as the mm-wave range. Due to high path loss for higher carrier frequencies, beamforming is an essential technology for mm-wave communication. Compared to analog beamforming, digital beamforming provides multiple simultaneous beams without an SNR penalty, is more accurate, enables faster steering, and provides full access to each element. Despite these advantages, digital beamforming has been limited by high power consumption, large die area, and the need for large numbers of analog-to-digital converters. Furthermore, beam squinting errors and ADC non-linearity limit the use of large digital beamforming arrays. We address these limitations. First, we address the power and area challenge by combining Interleaved Bit Stream Processing (IL-BSP) with power and area efficient Continuous-Time Band-Pass Delta-Sigma Modulators (CTBPDSMs). Compared to conventional DSP, IL-BSP reduces both power and area by 80%. Furthermore, the new CTBPDSM architecture reduces ADC area by 67% and the energy per conversion by 43% compared to previous work. Second, we introduce the first integrated digital true-time-delay digital beamforming receiver to resolve the beam squinting. True-time-delay beamforming eliminates squinting, making it an ideal choice for large-array wide-bandwidth applications. Third, we present a new current-steering DAC architecture that provides a constant output impedance to improve ADC linearity. This significantly reduces distortion, leading to an SFDR improvement of 13.7 dB from the array. Finally, we provide analysis to show that the ADC power consumption of a digital beamformer is comparable to that of the ADC power for an analog beamformer. To summarize, we present a prototype phased array and a prototype timed array, both with 16 elements, 4 independent beams, a 1 GHz center frequency, and a 100 MHz bandwidth. Both the phased array and timed array achieve nearly ideal conventional and adaptive beam patterns, including beam tapering and adaptive nulling. With an 11.2 dB array gain, the phased array achieves a 58.5 dB SNDR over a 100 MHz bandwidth, while consuming 312 mW and occupying 0.22 mm2. The timed array achieves an EVM better than -37 dB for 5 MBd QAM-256 and QAM-512, occupies only 0.29 mm2, and consumes 453 mW.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147716/1/smjang_1.pd

Design of a 14-bit fully differential discrete time delta-sigma modulator

Analog to digital converters play an essential role in modern mixed signal circuit design. Conventional Nyquist-rate converters require analog components that are precise and highly immune to noise and interference. In contrast, oversampling converters can be implemented using simple and high-tolerance analog components. Moreover, sampling at high frequency eliminates the need for abrupt cutoffs in the analog anti-aliasing filters. A noise shaping technique is also used in DS converters in addition to oversampling to achieve a high resolution conversion. A significant advantage of the method is that analog signals are converted using simple and high-tolerance analog circuits, usually a 1-bit comparator, and analog signal processing circuits having a precision that is usually much less than the resolution of the overall converter. In this thesis, a technique to design the discrete time DS converters for 25 kHz baseband signal bandwidth will be described. The noise shaping is achieved using a switched capacitor low-pass integrator around the 1-bit quantizer loop. A latched-type comparator is used as the quantizer of the DS converter. A second order DS modulator is implemented in a TSMC 0.35 µm CMOS technology using a 3.3 V power supply. The peak signal-to-noise ratio (SNR) simulated is 87 dB; the SNDR simulated is 82 dB which corresponds to a resolution of 14 bits. The total static power dissipation is 6.6 mW