Power Reductions with Energy Recovery Using Resonant Topologies

The problem of power densities in system-on-chips (SoCs) and processors has become more exacerbated recently, resulting in high cooling costs and reliability issues. One of the largest components of power consumption is the low skew clock distribution network (CDN), driving large load capacitance. This can consume as much as 70% of the total dynamic power that is lost as heat, needing elaborate sensing and cooling mechanisms. To mitigate this, resonant clocking has been utilized in several applications over the past decade. An improved energy recovering reconfigurable generalized series resonance (GSR) solution with all the critical support circuitry is developed in this work. This LC resonant clock driver is shown to save about 50% driver power (\u3e40% overall), on a 22nm process node and has 50% less skew than a non-resonant driver at 2GHz. It can operate down to 0.2GHz to support other energy savings techniques like dynamic voltage and frequency scaling (DVFS). As an example, GSR can be configured for the simpler pulse series resonance (PSR) operation to enable further power saving for double data rate (DDR) applications, by using de-skewing latches instead of flip-flop banks. A PSR based subsystem for 40% savings in clocking power with 40% driver active area reduction xii is demonstrated. This new resonant driver generates tracking pulses at each transition of clock for dual edge operation across DVFS. PSR clocking is designed to drive explicit-pulsed latches with negative setup time. Simulations using 45nm IBM/PTM device and interconnect technology models, clocking 1024 flip-flops show the reductions, compared to non-resonant clocking. DVFS range from 2GHz/1.3V to 200MHz/0.5V is obtained. The PSR frequency is set \u3e3× the clock rate, needing only 1/10th the inductance of prior-art LC resonance schemes. The skew reductions are achieved without needing to increase the interconnect widths owing to negative set-up times. Applications in data circuits are shown as well with a 90nm example. Parallel resonant and split-driver non-resonant configurations as well are derived from GSR. Tradeoffs in timing performance versus power, based on theoretical analysis, are compared for the first time and verified. This enables synthesis of an optimal topology for a given application from the GSR

Research on low power technology by AC power supply circuits

制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit

Modular multilevel converter with embedded battery cells for traction drives

This thesis proposes a new modular multilevel converter with embedded cell balancing for battery electric vehicles. In this topology, the battery cells are directly connected to the half-bridge choppers of the sub-modules, allowing the highest flexibility for the discharge and recharge of each individual cell. Tht: traditional battery management system is replaced by the control of the converter, which individually balances all the cells. A new balancing algorithm is presented and discussed in. the thesis, showing that the converter generates symmetric three-phase voltages with low harmonic distortion even for significantly unbalanced cells. The thesis also analyses stationary recharge of the battery cells from both three-phase and single-phase ac sources. The performance of the converter as a traction drive is assessed in terms of torque-speed characteristic and power losses for the full frequency range, including field weakening. A simplified model for estimating conduction and switching losses for the proposed modular multilevel converter is presented and the results for a typical driving cycle are compared with a traditional two-level converter. Simulation and experimental results on a kW-size prototype have confirmed the feasibility of the proposed traction modular converter in terms of effectiveness of the cell balancing control, validity of the proposed loss model, suitability of use for traction and effectiveness of recharging operations

Energy-Efficient Neural Network Architectures

Emerging systems for artificial intelligence (AI) are expected to rely on deep neural networks (DNNs) to achieve high accuracy for a broad variety of applications, including computer vision, robotics, and speech recognition. Due to the rapid growth of network size and depth, however, DNNs typically result in high computational costs and introduce considerable power and performance overheads. Dedicated chip architectures that implement DNNs with high energy efficiency are essential for adding intelligence to interactive edge devices, enabling them to complete increasingly sophisticated tasks by extending battery lie. They are also vital for improving performance in cloud servers that support demanding AI computations. This dissertation focuses on architectures and circuit technologies for designing energy-efficient neural network accelerators. First, a deep-learning processor is presented for achieving ultra-low power operation. Using a heterogeneous architecture that includes a low-power always-on front-end and a selectively-enabled high-performance back-end, the processor dynamically adjusts computational resources at runtime to support conditional execution in neural networks and meet performance targets with increased energy efficiency. Featuring a reconfigurable datapath and a memory architecture optimized for energy efficiency, the processor supports multilevel dynamic activation of neural network segments, performing object detection tasks with 5.3x lower energy consumption in comparison with a static execution baseline. Fabricated in 40nm CMOS, the processor test-chip dissipates 0.23mW at 5.3 fps. It demonstrates energy scalability up to 28.6 TOPS/W and can be configured to run a variety of workloads, including severely power-constrained ones such as always-on monitoring in mobile applications. To further improve the energy efficiency of the proposed heterogeneous architecture, a new charge-recovery logic family, called zero-short-circuit current (ZSCC) logic, is proposed to decrease the power consumption of the always-on front-end. By relying on dedicated circuit topologies and a four-phase clocking scheme, ZSCC operates with significantly reduced short-circuit currents, realizing order-of-magnitude power savings at relatively low clock frequencies (in the order of a few MHz). The efficiency and applicability of ZSCC is demonstrated through an ANSI S1.11 1/3 octave filter bank chip for binaural hearing aids with two microphones per ear. Fabricated in a 65nm CMOS process, this charge-recovery chip consumes 13.8µW with a 1.75MHz clock frequency, achieving 9.7x power reduction per input in comparison with a 40nm monophonic single-input chip that represents the published state of the art. The ability of ZSCC to further increase the energy efficiency of the heterogeneous neural network architecture is demonstrated through the design and evaluation of a ZSCC-based front-end. Simulation results show 17x power reduction compared with a conventional static CMOS implementation of the same architecture.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147614/1/hsiwu_1.pd

Optimizing the integration and energy efficiency of through silicon via-based 3D interconnects

The aggressive scaling of CMOS process technology has been driving the rapid growth of the semiconductor industry for more than three decades. In recent years, the performance gains enabled by CMOS scaling have been increasingly challenged by highlyparasitic on-chip interconnects as wire parasitics do not scale at the same pace. Emerging 3D integration technologies based on vertical through-silicon vias (TSVs) promise a solution to the interconnect performance bottleneck, along with reduced fabrication cost and heterogeneous integration. As TSVs are a relatively recent interconnect technology, innovative test structures are required to evaluate and optimise the process, as well as extract parameters for the generation of design rules and models. From the circuit designer’s perspective, critical TSV characteristics are its parasitic capacitance, and thermomechanical stress distribution. This work proposes new test structures for extracting these characteristics. The structures were fabricated on a 65nm 3D process and used for the evaluation of that technology. Furthermore, as TSVs are implemented in large, densely interconnected 3D-system-on-chips (SoCs), the TSV parasitic capacitance may become an important source of energy dissipation. Typical low-power techniques based on voltage scaling can be used, though this represents a technical challenge in modern technology nodes. In this work, a novel TSV interconnection scheme is proposed based on reversible computing, which shows frequencydependent energy dissipation. The scheme is analysed using theoretical modelling, while a demonstrator IC was designed based on the developed theory and fabricated on a 130nm 3D process.EThOS - Electronic Theses Online ServiceEngineering and Physical Science Research Council (EPSRC)GBUnited Kingdo

Contributions on DC microgrid supervision and control strategies for efficiency optimization through battery modeling, management, and balancing techniques

Aquesta tesi presenta equips, models i estratègies de control que han estat desenvolupats amb l'objectiu final de millorar el funcionament d'una microxarxa CC. Es proposen dues estratègies de control per a millorar l'eficiència dels convertidors CC-CC que interconnecten les unitats de potència de la microxarxa amb el bus CC. La primera estratègia, Control d'Optimització de Tensió de Bus centralitzat, administra la potència del Sistema d'Emmagatzematge d'Energia en Bateries de la microxarxa per aconseguir que la tensió del bus segueixi la referència dinàmica de tensió òptima que minimitza les pèrdues dels convertidors. La segona, Optimització en Temps Real de la Freqüència de Commutació, consisteix a operar localment cada convertidor a la seva freqüència de commutació òptima, minimitzant les seves pèrdues. A més, es proposa una nova topologia d'equilibrador actiu de bateries mitjançant un únic convertidor CC-CC i s'ha dissenyat la seva estratègia de control. El convertidor CC-CC transfereix càrrega cel·la a cel·la, emprant encaminament de potència a través d'un sistema d'interruptors controlats. L'estratègia de control de l'equalitzador aconsegueix un ràpid equilibrat del SOC evitant sobrecompensar el desequilibri. Finalment, es proposa un model simple de degradació d'una cel·la NMC amb elèctrode negatiu de grafit. El model combina la simplicitat d'un model de circuit equivalent, que explica la dinàmica ràpida de la cel·la, amb un model físic del creixement de la capa Interfase Sòlid-Electròlit (SEI), que prediu la pèrdua de capacitat i l'augment de la resistència interna a llarg termini. El model proposat quantifica la incorporació de liti al rang de liti ciclable necessària per a aconseguir els límits de OCV després de la pèrdua de liti ciclable en la reacció secundària. El model de degradació SEI pot emprar-se per a realitzar un control predictiu de bateries orientat a estendre la seva vida útil.Aquesta tesi presenta equips, models i estratègies de control que han estat desenvolupats amb l'objectiu final de millorar el funcionament d'una microxarxa CC. Es proposen dues estratègies de control per a millorar l'eficiència dels convertidors CC-CC que interconnecten les unitats de potència de la microxarxa amb el bus CC. La primera estratègia, Control d'Optimització de Tensió de Bus centralitzat, administra la potència del Sistema d'Emmagatzematge d'Energia en Bateries de la microxarxa per aconseguir que la tensió del bus segueixi la referència dinàmica de tensió òptima que minimitza les pèrdues dels convertidors. La segona, Optimització en Temps Real de la Freqüència de Commutació, consisteix a operar localment cada convertidor a la seva freqüència de commutació òptima, minimitzant les seves pèrdues. A més, es proposa una nova topologia d'equilibrador actiu de bateries mitjançant un únic convertidor CC-CC i s'ha dissenyat la seva estratègia de control. El convertidor CC-CC transfereix càrrega cel·la a cel·la, emprant encaminament de potència a través d'un sistema d'interruptors controlats. L'estratègia de control de l'equalitzador aconsegueix un ràpid equilibrat del SOC evitant sobrecompensar el desequilibri. Finalment, es proposa un model simple de degradació d'una cel·la NMC amb elèctrode negatiu de grafit. El model combina la simplicitat d'un model de circuit equivalent, que explica la dinàmica ràpida de la cel·la, amb un model físic del creixement de la capa Interfase Sòlid-Electròlit (SEI), que prediu la pèrdua de capacitat i l'augment de la resistència interna a llarg termini. El model proposat quantifica la incorporació de liti al rang de liti ciclable necessària per a aconseguir els límits de OCV després de la pèrdua de liti ciclable en la reacció secundària. El model de degradació SEI pot emprar-se per a realitzar un control predictiu de bateries orientat a estendre la seva vida útil.This dissertation presents a set of equipment, models and control strategies, that have been developed with the final goal of improving the operation of a DC microgrid. Two control strategies are proposed to improve the efficiency of the DC-DC converters that interface the microgrid’s power units with the DC bus. The first strategy is centralized Bus Voltage Optimization Control, which manages the power of the microgrid’s Battery Energy Storage System to make the bus voltage follow the optimum voltage dynamic reference that minimizes the converters’ losses. The second control strategy is Online Optimization of Switching Frequency, which consists in locally operating each converter at its optimum switching frequency, again minimizing power losses. The two proposed optimization strategies have been validated in simulations. Moreover, a new converter-based active balancing topology has been proposed and its control strategy has been designed. This equalizer topology consists of a single DC-DC converter that performs cell-to-cell charge transfer employing power routing via controlled switches. The control strategy of the equalizer has been designed to achieve rapid SOC balancing while avoiding imbalance overcompensation. Its performance has been validated in simulation. Finally, a simple degradation model of an NMC battery cell with graphite negative electrode is proposed. The model combines the simplicity of an equivalent circuit model, which explains the fast dynamics of the cell, with a physical model of the Solid-Electrolyte Interphase (SEI) layer growth process, which predicts the capacity loss and the internal resistance rise in the long term. The proposed model fine-tunes the capacity loss prediction by accounting for the incorporation of unused lithium reserves of both electrodes into the cyclable lithium range to reach the OCV limits after the side reaction has consumed cyclable lithium. The SEI degradation model can be used to perform predictive control of batteries oriented toward extending their lifetime

A low power, reconfigurable fabric body area network for healthcare applications

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 105-110).Body Area Networks (BANs) are gaining prominence for their capability to revolutionize medical monitoring, diagnosis and treatment. This thesis describes a BAN that uses conductive fabrics (e-textiles) worn by the user to act as a power distribution and data communication network to sensors on the user's body. The network is controlled by a central hub in the form of a Base Station, which can either be a standalone device or can be embedded inside one of the user's portable electronic devices like a cellphone. Specifications for a Physical (PHY) layer and a Medium Access Control (MAC) layer have been developed that make use of the asymmetric energy budgets between the base station and sensor nodes in the network. The PHY layer has been designed to be suitable for the unique needs of such a BAN, namely easy reconfigurability, fault-tolerance and efficient energy and data transfer at low power levels. This is achieved by a mechanism for dividing the network into groups of sensors. The co-designed MAC layer is capable of supporting a wide variety of sensors with different data rate and network access requirements, ranging from EEG monitors to temperature sensors. Circuits have been designed at both ends of the network to transmit, receive and store power and data in appropriate frequency bands. Digital circuits have been designed to implement the MAC protocols. The base station and sensor nodes have been implemented in standard 180nm 1P6M CMOS process, and occupy an area 4.8mm2 and 3.6mm2 respectively. The base station has a minimum power consumption of 2.86mW, which includes the power transmitter, modulation and demodulation circuitry. The sensor nodes can recover up to 33.6paW power to supply to the biomedical signal acquisition circuitry with peak transfer efficiency of 1.2%.by Nachiket Venkappayya Desai.S.M

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications