1-Bit Full Adder Circuit using XOR-XNOR Cells with Power and Area Optimization

This paper revel a realization of a superior circuit design of 1 bit full adder. The circuit is planned and implemented by using planar DG –MOSFETs at 45 nm technology. In CPU, arithmetic logic unit (ALU) is the core heart.   The adder cell is the important and necessary unit of an ALU. In the present paper, an improved 1-bit full adder circuit is proposed that consumes lower power and reduced number of transistors. The proposed adder circuit consists of 9 transistors and called as 9-T adder cell.  The planar DG-MOSFETs are new emerging transistors which can work n nanometer range and overcome the short channel effects. The simulation of proposed circuit is done in tanner tool version 13.0 using level 54 model files. The simulation is done to compare power, power delay product with supply voltage. The result is also checked at room temperature. This circuit performance of the proposed circuits compared with other reported circuits in literatures and it is seen approximately more than 99.9% reduction in power consumption. Keywords: Low power; Area Efficent; Full Adder; GDI; Multiplexer

Implementation of Full Adder Circuit using Stack Technique

This paper presents a design of a one bit full adder cell based on stack effect using Double Gate MOSFET. This design has been compared with existing one-bit full adder which is designed using power gating technique.  In this paper, the proposed circuit has been analyzed for parameters like- power consumption and power delay product. The simulations of the proposed Full Adder have been performed using Tanner EDA Tool version 16.1. All the proposed design simulations are carried out at 45nm technology for various inputs like supply voltage and input voltage. The decrease of 91.1% in power utilization has observed in proposed circuit. The results show a legality of double gate MOSFETs for designing for low power full adder circuit. Keywords: DG-MOSFET, ALU, XOR, Full Adder,PTI, GDI, Diffused Gdi,Finfet, ELK, Power Grating , Stacking

Design of New High-Performance Full Adder Using Hybrid-CMOS Logic Style for High-Speed Applications

This paper, presents a new design for 1-bit full adder cell using hybrid-CMOS logic style. Using a novel structure for implementation of the proposed full adder caused it has better performance in terms of propagation delay and power-delay product (PDP) compared to its counterparts. According to the simulation results, the propagation delay of the proposed full adder is 22.8% less than the propagation delay of next fastest full adder, and the power-delay product of the proposed full adder is 22.7% less than the next best PDP. HSpice simulations using 65nm technology with a power supply of 1.2V was utilized to evaluate the performance of the circuits

Simulation and Modeling of Silicon Based Emerging Nanodevices: From Device to Circuit Level

Nanostructure based devices are very promising candidates for the emerging nanotechnologies with advantage in terms of power consumption and functional density. Nanowire Field Effect Transistor (NWFET) and Single Electron Transistor (SET) are the focus of this work. The serious challenges faced by the MOSFET due to scaling limits can be solved by these devices. NWFET provides better gate control and overcomes the short channel effects. SET operates in the quantum confinement regime where the basic operation of MOSFET becomes a challenge. SET works better when the dimensions are small encouraging the process of scaling down. Because of these characteristics of the nanodevices, they have achieved a huge interest from the viewpoint of theoretical as well as applied electronics. The studies focus on the understanding of the basic transport characteristics of the devices. The necessity is to develop a model which is efficient, can be used at circuit level and also provides physical insights of the device. The first part of this work focuses on developing the model for SET and to implement it at the circuit level. The transport properties of SET are studied through quantum simulations. The behavioral characterization of the device is performed and the effect of different device parameters on the transport is studied. Furthermore, the impact of gate voltage is analyzed which modulates the current by shifting the energy levels of the device. After observing the transport through SET, a model is developed that efficiently evaluates the IV characteristics of the device. The quantum simulations are used as reference and a huge computational over-head is achieved while maintaining accuracy. Then the model is implemented in hardware descriptive language showing its functional variability at circuit level by designing some logic circuits like AND, OR and FA. In the second part, the performance of the nanoarrays based on NWFET is characterized. A device level model is developed to evaluate the gate capacitance and drain current of NWFET. Starting from the output of the model, in-house simulator is modified and used to evaluate the switching activity of the devices in nanoarray. A nanoarray implementation for bio-sequence alignment based on a systolic array is realized and its essential performance is evaluated. The power consumption, area and performance of the nanoarray implementation are compared with CMOS implementation. A wide solution space can be explored to find the optimal solution trading power and performance and considering the technological limitations of a realistic implementation

A novel asynchronous control unit and the application to a pipelined multiplier

[[abstract]]This paper discusses the technique for asynchronous circuit design using a novel asynchronous control unit. We employ the very commonly used device, pass-transistor multiplexer, to design and implement the asynchronous control unit. Even though the architecture of the control unit is simple, the efficiency is good. A multiplier with pipelined structure has been designed to verify the usefulness of this technique. We use TSMC's 0.6 μm SPDM process to design and implement an 8-b×8-b pipelined multiplier. The HSPICE simulation shows that the feedthrough rate of the inputs can be as high as 250 MHz.[[conferencetype]]國際[[conferencedate]]19980531~19980603[[booktype]]紙

Architectural level delay and leakage power modelling of manufacturing process variation

PhD ThesisThe effect of manufacturing process variations has become a major issue regarding the estimation of circuit delay and power dissipation, and will gain more importance in the future as device scaling continues in order to satisfy market place demands for circuits with greater performance and functionality per unit area. Statistical modelling and analysis approaches have been widely used to reflect the effects of a variety of variational process parameters on system performance factor which will be described as probability density functions (PDFs). At present most of the investigations into statistical models has been limited to small circuits such as a logic gate. However, the massive size of present day electronic systems precludes the use of design techniques which consider a system to comprise these basic gates, as this level of design is very inefficient and error prone. This thesis proposes a methodology to bring the effects of process variation from transistor level up to architectural level in terms of circuit delay and leakage power dissipation. Using a first order canonical model and statistical analysis approach, a statistical cell library has been built which comprises not only the basic gate cell models, but also more complex functional blocks such as registers, FIFOs, counters, ALUs etc. Furthermore, other sensitive factors to the overall system performance, such as input signal slope, output load capacitance, different signal switching cases and transition types are also taken into account for each cell in the library, which makes it adaptive to an incremental circuit design. The proposed methodology enables an efficient analysis of process variation effects on system performance with significantly reduced computation time compared to the Monte Carlo simulation approach. As a demonstration vehicle for this technique, the delay and leakage power distributions of a 2-stage asynchronous micropipeline circuit has been simulated using this cell library. The experimental results show that the proposed method can predict the delay and leakage power distribution with less than 5% error and at least 50,000 times faster computation time compare to 5000-sample SPICE based Monte Carlo simulation. The methodology presented here for modelling process variability plays a significant role in Design for Manufacturability (DFM) by quantifying the direct impact of process variations on system performance. The advantages of being able to undertake this analysis at a high level of abstraction and thus early in the design cycle are two fold. First, if the predicted effects of process variation render the circuit performance to be outwith specification, design modifications can be readily incorporated to rectify the situation. Second, knowing what the acceptable limits of process variation are to maintain design performance within its specification, informed choices can be made regarding the implementation technology and manufacturer selected to fabricate the design

Layout Design of 32-bit Brent Kung Adder (Cmos Logic)

Adders play a key role in the arithmetic circuits. These arithmetic circuits perform operations like addition, subtraction, multiplication, division, parity calculation etc. The performance of the microprocessors mainly depends upon the speed of the response of these arithmetic operations. Apart from the arithmetic operations the adders are also used for calculating the addresses, tables and similar operations. It is also used in digital signal processor (DSP). As adder is the main circuit, the performance depends on its functioning or speed. Improving its performance is the main area of research in VLSI system design. The conventional adders may work well for small number of bits but when the length increases (say 32-bit, 64-bit, 128-bit and so on) the performance of the conventional adders degrades. Thus in industries tree adders or parallel prefix adders are used for arithmetic operations. There are 6 types of tree adders. Here in this work the layout of 32-bit Brent Kung adder is designed and its delay is calculated. The layouts of 16-bit Brent Kung, Sklansky, Kogge Stone adders are also designed and their delays are compared. The critical path for all these tree adders is computed. For designing these layouts the software used is �magic layout tool� and outputs are verified using �IRSIM�. Minimum transistor width (5lambda) is used in these designs.Electrical Engineerin

Design of Digital Circuits at Transistor Level

Práce se zaměřuje na návrh obvodů na úrovni tranzistorů, především za použití evoluční metody návrhu. Za tímto účelem je nutné volit rozumnou míru abstrakce a tak dosáhnout vyšší rychlosti ohodnocování kandidátních řešení pomocí fitness funkce. Práce probírá již vyzkoušené postupy návrhu obvodů na tranzistorové úrovni a z nich vybírá užitečné prvky pro vytvoření výkonějšího systému, který by byl schopen navrhovat komplexní logické obvody. Dále se práce zabývá implementací tohoto systému a probírá použitý přístup k řešení problémů návrhu a optimilizace tranzistorových obvodů použitím evoluce.This work aims to design process of integrated circuits on the transistor level, specially using evolutionary algorithm. For this purpose it is necessary to choose reasonable level of abstraction during simulation, which is used for evaluation candidate solutions by fitness function. This simulation has to be fast enough to evaluate thousands of candidate solutions within seconds. This work discusses already used techniques for transistor level circuit design and it chooses useful parts for new design of faster and more reliable automated design process, which would be able to design complex logic circuits. The thesis also discusses implementation of this system and used approach with regard to encountered problems in transistor-level circuit design and optimization by evolution.

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Generating efficient layouts from optimized MOS circuit schematics

Also issued as Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1988.Includes bibliographical references.Supported by the U.S. Air Force--Office of Scientific Research. AFOSR-86-0164 Supported in part by a National Science Foundation Graduate Fellowship. Supported in part by Thinking Machines Corporation. 2305/B4Donald George Baltus