Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio

A discrete-time (DT) mixing architecture for RF-sampling receivers is presented. This architecture makes RF sampling more suitable for software-defined radio (SDR) as it achieves wideband quadrature demodulation and wideband harmonic rejection. The paper consists of two parts. In the first part, different downconversion techniques are classified and compared, leading to the definition of a DT mixing concept. The suitability of CT-mixing and RF-sampling receivers to SDR is also discussed. In the second part, we elaborate the DT-mixing architecture, which can be realized by de-multiplexing. Simulation shows a wideband 90° phase shift between I and Q outputs without systematic channel bandwidth limitation. Oversampling and harmonic rejection relaxes RF pre-filtering and reduces noise and interference folding. A proof-of-concept DT-mixing downconverter has been built in 65 nm CMOS, for 0.2 to 0.9 GHz RF band employing 8-times oversampling. It can reject 2nd to 6th harmonics by 40 dB typically and without systematic channel bandwidth limitation. Without an LNA, it achieves a gain of -0.5 to 2.5 dB, a DSB noise figure of 18 to 20 dB, an IIP3 = +10 dBm, and an IIP2 = +53 dBm, while consuming less than 19 mW including multiphase clock generation

Digitally-Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference

A software-defined radio (SDR) receiver with improved robustness to out-of-band interference (OBI) is presented. Two main challenges are identified for an OBI-robust SDR receiver: out-of-band nonlinearity and harmonic mixing. Voltage gain at RF is avoided, and instead realized at baseband in combination with low-pass filtering to mitigate blockers and improve out-of-band IIP3. Two alternative “iterative” harmonic-rejection (HR) techniques are presented to achieve high HR robust to mismatch: a) an analog two-stage polyphase HR concept, which enhances the HR to more than 60 dB; b) a digital adaptive interference cancelling (AIC) technique, which can suppress one dominating harmonic by at least 80 dB. An accurate multiphase clock generator is presented for a mismatch-robust HR. A proof-of-concept receiver is implemented in 65 nm CMOS. Measurements show 34 dB gain, 4 dB NF, and 3.5 dBm in-band IIP3 while the out-of-band IIP3 is + 16 dBm without fine tuning. The measured RF bandwidth is up to 6 GHz and the 8-phase LO works up to 0.9 GHz (master clock up to 7.2 GHz). At 0.8 GHz LO, the analog two-stage polyphase HR achieves a second to sixth order HR > dB over 40 chips, while the digital AIC technique achieves HR > 80 dB for the dominating harmonic. The total power consumption is 50 mA from a 1.2 V supply

Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 μm CMOS technology validate the proposed technique

Python modelling of the SX1257 transceiver

The main purpose of this project is to create a python model of the SX1257 transceiver by Semtech and everything has been prepared in order to be able to compare the model with the real component in the near future. The ultimate goal is to have a simulation model that can be used to develop FPGA SDR designs, for example by cosimulating the HDL code with the python model using the cocotb cosimulation framework.Universidad de Sevilla. Grado en Ingeniería de las Tecnologías de Telecomunicación

A 1.2V wide-band reconfigurable mixer for wireless application in 65nm CMOS technology

This paper presents a wideband (WB) reconfigurable down-conversion mixer for multi-standard wireless receivers. The proposed mixer is re-configurable between active mixer and passive mixer modes. Reconfigurability is made through switching the input signal between gate and source terminal of input transistors and enabling/disabling the transimpedance stage at the output. The CMOS transmission gate (TG) switches are designed to provide optimum headroom in this low voltage design. The proposed circuit is designed in UMC 65nm RFCMOS technology with 1.2V supply voltage. From the simulation results, the proposed circuit shows conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.6 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. Hence this circuit will be much helpful in multi-standard receiver design in IoT perspective

GNSS array-based acquisition: theory and implementation

This Dissertation addresses the signal acquisition problem using antenna arrays in the general framework of Global Navigation Satellite Systems (GNSS) receivers. The term GNSS classi es those navigation systems based on a constellation of satellites, which emit ranging signals useful for positioning. Although the American GPS is already available, which coexists with the renewed Russian Glonass, the forthcoming European contribution (Galileo) along with the Chinese Compass will be operative soon. Therefore, a variety of satellite constellations and signals will be available in the next years. GNSSs provide the necessary infrastructures for a myriad of applications and services that demand a robust and accurate positioning service. The positioning availability must be guaranteed all the time, specially in safety-critical and mission-critical services. Examining the threats against the service availability, it is important to take into account that all the present and the forthcoming GNSSs make use of Code Division Multiple Access (CDMA) techniques. The ranging signals are received with very low precorrelation signal-to-noise ratio (in the order of ���22 dB for a receiver operating at the Earth surface). Despite that the GNSS CDMA processing gain o ers limited protection against Radio Frequency interferences (RFI), an interference with a interference-to-signal power ratio that exceeds the processing gain can easily degrade receivers' performance or even deny completely the GNSS service, specially conventional receivers equipped with minimal or basic level of protection towards RFIs. As a consequence, RFIs (either intentional or unintentional) remain as the most important cause of performance degradation. A growing concern of this problem has appeared in recent times. Focusing our attention on the GNSS receiver, it is known that signal acquisition has the lowest sensitivity of the whole receiver operation, and, consequently, it becomes the performance bottleneck in the presence of interfering signals. A single-antenna receiver can make use of time and frequency diversity to mitigate interferences, even though the performance of these techniques is compromised in low SNR scenarios or in the presence of wideband interferences. On the other hand, antenna arrays receivers can bene t from spatial-domain processing, and thus mitigate the e ects of interfering signals. Spatial diversity has been traditionally applied to the signal tracking operation of GNSS receivers. However, initial tracking conditions depend on signal acquisition, and there are a number of scenarios in which the acquisition process can fail as stated before. Surprisingly, to the best of our knowledge, the application of antenna arrays to GNSS signal acquisition has not received much attention. This Thesis pursues a twofold objective: on the one hand, it proposes novel arraybased acquisition algorithms using a well-established statistical detection theory framework, and on the other hand demonstrates both their real-time implementation feasibility and their performance in realistic scenarios. The Dissertation starts with a brief introduction to GNSS receivers fundamentals, providing some details about the navigation signals structure and the receiver's architecture of both GPS and Galileo systems. It follows with an analysis of GNSS signal acquisition as a detection problem, using the Neyman-Pearson (NP) detection theory framework and the single-antenna acquisition signal model. The NP approach is used here to derive both the optimum detector (known as clairvoyant detector ) and the sov called Generalized Likelihood Ratio Test (GLRT) detector, which is the basis of almost all of the current state-of-the-art acquisition algorithms. Going further, a novel detector test statistic intended to jointly acquire a set of GNSS satellites is obtained, thus reducing both the acquisition time and the required computational resources. The eff ects of the front-end bandwidth in the acquisition are also taken into account. Then, the GLRT is extended to the array signal model to obtain an original detector which is able to mitigate temporally uncorrelated interferences even if the array is unstructured and moderately uncalibrated, thus becoming one of the main contributions of this Dissertation. The key statistical feature is the assumption of an arbitrary and unknown covariance noise matrix, which attempts to capture the statistical behavior of the interferences and other non-desirable signals, while exploiting the spatial dimension provided by antenna arrays. Closed form expressions for the detection and false alarm probabilities are provided. Performance and interference rejection capability are modeled and compared both to their theoretical bound. The proposed array-based acquisition algorithm is also compared to conventional acquisition techniques performed after blind null-steering beamformer approaches, such as the power minimization algorithm. Furthermore, the detector is analyzed under realistic conditions, accounting for the presence of errors in the covariance matrix estimation, residual Doppler and delay errors, and signal quantization e ects. Theoretical results are supported by Monte Carlo simulations. As another main contribution of this Dissertation, the second part of the work deals with the design and the implementation of a novel Field Programmable Gate Array (FPGA)-based GNSS real-time antenna-array receiver platform. The platform is intended to be used as a research tool tightly coupled with software de ned GNSS receivers. A complete signal reception chain including the antenna array and the multichannel phase-coherent RF front-end for the GPS L1/ Galileo E1 was designed, implemented and tested. The details of the digital processing section of the platform, such as the array signal statistics extraction modules, are also provided. The design trade-o s and the implementation complexities were carefully analyzed and taken into account. As a proof-of-concept, the problem of GNSS vulnerability to interferences was addressed using the presented platform. The array-based acquisition algorithms introduced in this Dissertation were implemented and tested under realistic conditions. The performance of the algorithms were compared to single antenna acquisition techniques, measured under strong in-band interference scenarios, including narrow/wide band interferers and communication signals. The platform was designed to demonstrate the implementation feasibility of novel array-based acquisition algorithms, leaving the rest of the receiver operations (mainly, tracking, navigation message decoding, code and phase observables, and basic Position, Velocity and Time (PVT) solution) to a Software De ned Radio (SDR) receiver running in a personal computer, processing in real-time the spatially- ltered signal sample stream coming from the platform using a Gigabit Ethernet bus data link. In the last part of this Dissertation, we close the loop by designing and implementing such software receiver. The proposed software receiver targets multi-constellation/multi-frequency architectures, pursuing the goals of e ciency, modularity, interoperability, and exibility demanded by user domains that require non-standard features, such as intermediate signals or data extraction and algorithms interchangeability. In this context, we introduce an open-source, real-time GNSS software de ned receiver (so-named GNSS-SDR) that contributes with several novel features such as the use of software design patterns and shared memory techniques to manage e ciently the data ow between receiver blocks, the use of hardware-accelerated instructions for time-consuming vector operations like carrier wipe-o and code correlation, and the availability to compile and run on multiple software platforms and hardware architectures. At this time of writing (April 2012), the receiver enjoys of a 2-dimensional Distance Root Mean Square (DRMS) error lower than 2 meters for a GPS L1 C/A scenario with 8 satellites in lock and a Horizontal Dilution Of Precision (HDOP) of 1.2.Esta tesis aborda el problema de la adquisición de la señal usando arrays de antenas en el marco general de los receptores de Sistemas Globales de Navegación por Satélite (GNSS). El término GNSS engloba aquellos sistemas de navegación basados en una constelación de satélites que emiten señales útiles para el posicionamiento. Aunque el GPS americano ya está disponible, coexistiendo con el renovado sistema ruso GLONASS, actualmente se está realizando un gran esfuerzo para que la contribución europea (Galileo), junto con el nuevo sistema chino Compass, estén operativos en breve. Por lo tanto, una gran variedad de constelaciones de satélites y señales estarán disponibles en los próximos años. Estos sistemas proporcionan las infraestructuras necesarias para una multitud de aplicaciones y servicios que demandan un servicio de posicionamiento confiable y preciso. La disponibilidad de posicionamiento se debe garantizar en todo momento, especialmente en los servicios críticos para la seguridad de las personas y los bienes. Cuando examinamos las amenazas de la disponibilidad del servicio que ofrecen los GNSSs, es importante tener en cuenta que todos los sistemas presentes y los sistemas futuros ya planificados hacen uso de técnicas de multiplexación por división de código (CDMA). Las señales transmitidas por los satélites son recibidas con una relación señal-ruido (SNR) muy baja, medida antes de la correlación (del orden de -22 dB para un receptor ubicado en la superficie de la tierra). A pesar de que la ganancia de procesado CDMA ofrece una protección inherente contra las interferencias de radiofrecuencia (RFI), esta protección es limitada. Una interferencia con una relación de potencia de interferencia a potencia de la señal que excede la ganancia de procesado puede degradar el rendimiento de los receptores o incluso negar por completo el servicio GNSS. Este riesgo es especialmente importante en receptores convencionales equipados con un nivel mínimo o básico de protección frente las RFIs. Como consecuencia, las RFIs (ya sean intencionadas o no intencionadas), se identifican como la causa más importante de la degradación del rendimiento en GNSS. El problema esta causando una preocupación creciente en los últimos tiempos, ya que cada vez hay más servicios que dependen de los GNSSs Si centramos la atención en el receptor GNSS, es conocido que la adquisición de la señal tiene la menor sensibilidad de todas las operaciones del receptor, y, en consecuencia, se convierte en el factor limitador en la presencia de señales interferentes. Un receptor de una sola antena puede hacer uso de la diversidad en tiempo y frecuencia para mitigar las interferencias, aunque el rendimiento de estas técnicas se ve comprometido en escenarios con baja SNR o en presencia de interferencias de banda ancha. Por otro lado, los receptores basados en múltiples antenas se pueden beneficiar del procesado espacial, y por lo tanto mitigar los efectos de las señales interferentes. La diversidad espacial se ha aplicado tradicionalmente a la operación de tracking de la señal en receptores GNSS. Sin embargo, las condiciones iniciales del tracking dependen del resultado de la adquisición de la señal, y como hemos visto antes, hay un número de situaciones en las que el proceso de adquisición puede fallar. En base a nuestro grado de conocimiento, la aplicación de los arrays de antenas a la adquisición de la señal GNSS no ha recibido mucha atención, sorprendentemente. El objetivo de esta tesis doctoral es doble: por un lado, proponer nuevos algoritmos para la adquisición basados en arrays de antenas, usando como marco la teoría de la detección de señal estadística, y por otro lado, demostrar la viabilidad de su implementación y ejecución en tiempo real, así como su medir su rendimiento en escenarios realistas. La tesis comienza con una breve introducción a los fundamentos de los receptores GNSS, proporcionando algunos detalles sobre la estructura de las señales de navegación y la arquitectura del receptor aplicada a los sistemas GPS y Galileo. Continua con el análisis de la adquisición GNSS como un problema de detección, aplicando la teoría del detector Neyman-Pearson (NP) y el modelo de señal de una única antena. El marco teórico del detector NP se utiliza aquí para derivar tanto el detector óptimo (conocido como detector clarividente) como la denominada Prueba Generalizada de la Razón de Verosimilitud (en inglés, Generalized Likelihood Ratio Test (GLRT)), que forma la base de prácticamente todos los algoritmos de adquisición del estado del arte actual. Yendo más lejos, proponemos un nuevo detector diseñado para adquirir simultáneamente un conjunto de satélites, por lo tanto, obtiene una reducción del tiempo de adquisición y de los recursos computacionales necesarios en el proceso, respecto a las técnicas convencionales. El efecto del ancho de banda del receptor también se ha tenido en cuenta en los análisis. A continuación, el detector GLRT se extiende al modelo de señal de array de antenas para obtener un detector nuevo que es capaz de mitigar interferencias no correladas temporalmente, incluso utilizando arrays no estructurados y moderadamente descalibrados, convirtiéndose así en una de las principales aportaciones de esta tesis. La clave del detector es asumir una matriz de covarianza de ruido arbitraria y desconocida en el modelo de señal, que trata de captar el comportamiento estadístico de las interferencias y otras señales no deseadas, mientras que utiliza la dimensión espacial proporcionada por los arrays de antenas. Se han derivado las expresiones que modelan las probabilidades teóricas de detección y falsa alarma. El rendimiento del detector y su capacidad de rechazo a interferencias se han modelado y comparado con su límite teórico. El algoritmo propuesto también ha sido comparado con técnicas de adquisición convencionales, ejecutadas utilizando la salida de conformadores de haz que utilizan algoritmos de filtrado de interferencias, como el algoritmo de minimización de la potencia. Además, el detector se ha analizado bajo condiciones realistas, representadas con la presencia de errores en la estimación de covarianzas, errores residuales en la estimación del Doppler y el retardo de señal, y los efectos de la cuantificación. Los resultados teóricos se apoyan en simulaciones de Monte Carlo. Como otra contribución principal de esta tesis, la segunda parte del trabajo trata sobre el diseño y la implementación de una nueva plataforma para receptores GNSS en tiempo real basados en array de antenas que utiliza la tecnología de matriz programable de puertas lógicas (en ingles Field Programmable Gate Array (FPGA)). La plataforma está destinada a ser utilizada como una herramienta de investigación estrechamente acoplada con receptores GNSS definidos por software. Se ha diseñado, implementado y verificado la cadena completa de recepción, incluyendo el array de antenas y el front-end multi-canal para las señales GPS L1 y Galileo E1. El documento explica en detalle el procesado de señal que se realiza, como por ejemplo, la implementación del módulo de extracción de estadísticas de la señal. Los compromisos de diseño y las complejidades derivadas han sido cuidadosamente analizadas y tenidas en cuenta. La plataforma ha sido utilizada como prueba de concepto para solucionar el problema presentado de la vulnerabilidad del GNSS a las interferencias. Los algoritmos de adquisición introducidos en esta tesis se han implementado y probado en condiciones realistas. El rendimiento de los algoritmos se comparó con las técnicas de adquisición basadas en una sola antena. Se han realizado pruebas en escenarios que contienen interferencias dentro de la banda GNSS, incluyendo interferencias de banda estrecha y banda ancha y señales de comunicación. La plataforma fue diseñada para demostrar la viabilidad de la implementación de nuevos algoritmos de adquisición basados en array de antenas, dejando el resto de las operaciones del receptor (principalmente, los módulos de tracking, decodificación del mensaje de navegación, los observables de código y fase, y la solución básica de Posición, Velocidad y Tiempo (PVT)) a un receptor basado en el concepto de Radio Definida por Software (SDR), el cual se ejecuta en un ordenador personal. El receptor procesa en tiempo real las muestras de la señal filltradas espacialmente, transmitidas usando el bus de datos Gigabit Ethernet. En la última parte de esta Tesis, cerramos ciclo diseñando e implementando completamente este receptor basado en software. El receptor propuesto está dirigido a las arquitecturas de multi-constalación GNSS y multi-frecuencia, persiguiendo los objetivos de eficiencia, modularidad, interoperabilidad y flexibilidad demandada por los usuarios que requieren características no estándar, tales como la extracción de señales intermedias o de datos y intercambio de algoritmos. En este contexto, se presenta un receptor de código abierto que puede trabajar en tiempo real, llamado GNSS-SDR, que contribuye con varias características nuevas. Entre ellas destacan el uso de patrones de diseño de software y técnicas de memoria compartida para administrar de manera eficiente el uso de datos entre los bloques del receptor, el uso de la aceleración por hardware para las operaciones vectoriales más costosas, como la eliminación de la frecuencia Doppler y la correlación de código, y la disponibilidad para compilar y ejecutar el receptor en múltiples plataformas de software y arquitecturas de hardware. A fecha de la escritura de esta Tesis (abril de 2012), el receptor obtiene un rendimiento basado en la medida de la raíz cuadrada del error cuadrático medio en la distancia bidimensional (en inglés, 2-dimensional Distance Root Mean Square (DRMS) error) menor de 2 metros para un escenario GPS L1 C/A con 8 satélites visibles y una dilución de la precisión horizontal (en inglés, Horizontal Dilution Of Precision (HDOP)) de 1.2

Architectures and Circuit Techniques for High-Performance Field-Programmable CMOS Software Defined Radios

Next-generation wireless communication systems put more stringent performance requirements on the wireless RF receiver circuits. Sensitivity, linearity, bandwidth and power consumption are some of the most important specifications that often face tightly coupled tradeoffs between them. To increase the data throughput, a large number of fragmented spectrums are being introduced to the wireless communication standards. Carrier aggregation technology needs concurrent communication across several non-contiguous frequency bands, which results in a rapidly growing number of band combinations. Supporting all the frequency bands and their aggregation combinations increases the complexity of the RF receivers. Highly flexible software defined radio (SDR) is a promising technology to address these applications scenarios with lower complexity by relaxing the specifications of the RF filters or eliminating them. However, there are still many technology challenges with both the receiver architecture and the circuit implementations. The performance requirements of the receivers can also vary across different application scenario and RF environments. Field-programmable dynamic performance tradeoff can potentially reduce the power consumption of the receiver. In this dissertation, we address the performance enhancement challenges in the wideband SDRs by innovations at both the circuit building block level and the receiver architecture level. A series of research projects are conducted to push the state-of-the-art performance envelope and add features such as field-programmable performance tradeoff and concurrent reception. The projects originate from the concept of thermal noise canceling techniques and further enhance the RF performance and add features for more capable SDR receivers. Four generations of prototype LNA or receiver chips are designed, and each of them pushes at least one aspect of the RF performance such as bandwidth, linearity, and NF. A noise-canceling distributed LNA breaks the tradeoff between NF and RF bandwidth by introducing microwave circuit techniques from the distributed amplifiers. The LNA architecture uniquely provides ultra high bandwidth and low NF at low frequencies. A family of field-programmable LNA realized field-programmable performance tradeoff with current-reuse programmable transconductance cells. Interferer-reflecting loops can be applied around the LNAs to improve their input linearity by rejecting the out-of-band interferers with a wideband low in- put impedance. A low noise transconductance amplifier (LNTA) that operates in class-AB-C is invented to can handle rail-to-rail out-of-band blocker without saturation. Class-AB and class-C transconductors form a composite amplifier to increase the linear range of the input voltage. A new antenna interface named frequency-translational quadrature-hybrid (FTQH) breaks the input impedance matching requirement of the LNAs by introducing quadrature hybrid couplers to the CMOS RFIC design. The FTQH receiver achieves wideband sub-1dB NF and supports scalable massive frequency-agile concurrent reception

Circuits and architectures for broadband spectrum channelizers with sub-band gain control

Broadband receiver architectures for full-band or concurrent multi-band reception of signals are required in several applications. One approach to implementing such receivers is a spectrum channelizer that employs a frequency-folded analog-to-digital converter (FF-ADC). The design downconverts and channelizes a broadband input signal into multiple sub-bands at baseband by employing the harmonics of non-overlapping rectangular clocks. The downconverted and aliased baseband signal in each path is digitized by a baseband ADC, referred to as a sub-ADC below, that operates with a sampling rate that is lower than the Nyquist sampling rate set by the full bandwidth of the input signal. Sub-band separation is performed through digital harmonic rejection (HR) and image rejection (IR). The design operates similar to a time-interleaved ADC, except that it significantly reduces the bandwidth requirement of the samplers. If rectangular pulse waveforms are used in the FF-ADC down-converter, all sub-bands experience nearly equal gain during frequency down-conversion. Since all sub-bands are aliased to baseband before they are separated in the digital domain, a sub-band with large relative power can reduce the sub-ADC dynamic range that is available for other sub-bands, in addition to appearing as a blocker for other sub-bands. The research presented in this dissertation addresses approaches to overcome this issue, by embedding sub-band gain control within an FF-ADC. Chapter 2 proposes an approach that employs pulse-width-modulated local oscillator (PWM-LO) waveforms in the polyphase paths of an FF-ADC for scaling individual sub-band signal levels at baseband before digitization. The PWM-LO waveforms, which directly drive switches in each path, can be used to vary the gain in each sub-band by varying the level of harmonics in the waveforms. This is achieved by controlling the pulse-widths of the PWM-LO waveforms. This design avoids the requirement for N ×N switch matrices and variable transconductance cells in prior demonstrated approaches. The proposed architecture makes it possible to vary the spectral response of the FF-ADC with low signal-path complexity. Prediction of pulse widths for the desired harmonic, and hence the gain profile across all sub-bands, is performed using an off-chip supervised learning approach employing a neural network. Chapter 3 presents the implementation of a spectrum channelizer employing the PWM-LO-based sub-band amplitude control. The design allows for scaling the relative gain of the sub-bands over a 20-dB range. This relaxes the compression performance of the channelizer baseband and the sub-ADC dynamic range in the presence of sub-bands with significantly higher signal levels. Gain control on individual sub-bands is performed by employing customized PWM-LO waveforms,where the PWM-LO pulses are generated using delay-locked loops (DLLs). The off-chip neural-network based learning technique for estimating the PWM symbol pulse widths required for setting the desired LO harmonic levels is described. A 1.6 GS/s spectrum channelizer IC is implemented in a 65-nm CMOS process to verify the architecture. The measured channelizer gain is 51.6-56.5 dB without gain scaling and provides a range of 37-59 dB with PWM-LO gain control. Gain-scaling at a specific harmonic improves blocker compression in an unattenuated sub-band from -34 dBm to -16 dBm. The in-band gain compression with gain-scaling also increases from -32 dBm to -17 dBm. Chapter 4 describes a spectrum channelizer that uses voltage-mode downconversion. The approach requires a single voltage-mode input amplifier to drive the downconversion switches. Frequency-folding and sub-band gain control are achieved in a single signal path. This contrasts with the current-mode approach that requires a main FF-ADC path and a separate auxiliary path for sub-band gain control. By avoiding the requirement for an auxiliary input path, the approach presented here significantly simplifies the signal chain with identical gain-scaling capability. The contributions of this research and scope for future related work are summarized in Chapter 5.Electrical and Computer Engineerin