781 research outputs found
3중 샘플링 방식 델타-시그마 ADC를 이용한 디지털 Capacitive MEMS 마이크로폰
학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022. 8. 김수환.본 논문에서는 트리플 샘플링 적분기를 사용한 Capacitive 방식의 MEMS 마이크로폰이 제시되었다. 트리플 샘플링은 델타-시그마 방식의 아날로그-디지털 변환기의 첫 번째 적분기에 사용되었고 크게 두 가지의 동작으로 구분된다. 첫 번째로 적분기의 입력에서 반주기 지연 차동 입력을 빼서 신호 크기를 2배로 만들는 방식. 두 번째로 DAC의 피드백 커패시터를 샘플링 커패시터로 사용하여 입력 전압을 추가로 증가시키는 방식이다. 추가적으로 기존에서 샘플링 커패시터를 증가시켜 신호의 크기를 증폭시키는 방식과 결합하여 실수배의 이득을 얻을 수 있다. 또한 추가적인 커패시터, 타이밍, 전류 소모 없이 구조 변경만으로 이를 달성하였기 때문에 별다른 trade-off 없이 신호의 크기를 증폭시킬 수 있었다. 추가적으로 트리플 샘플링 방식의 적분기 신호 전달 함수 및 잡음 분석 또한 포함하였다.
우리의 readout 회로는 공급 전압이 1.8V인 0.18 m CMOS 공정으로 구현하였고 single-ended capacitive MEMS 트랜스듀서를 사용하여 측정하였다. 전류 소모량은 520 μA 이다. 마이크로폰은 A-weighted 신호 대 잡음 비는 62.1 dBA, 음향 과부하 지점은 115 dB SPL을 달성하였고 칩의 die size는 0.98〖"mm" 〗^2 이다.A triple-sampling ΔΣ ADC can replace the programmable-gain amplifier commonly used in the readout circuit for a digital capacitive MEMS microphone. The input voltage can then be multiplied by subtracting a further half-period delayed differential input and using the feedback capacitor of the DAC as a sampling capacitor. This triple-sampling technique results in a readout circuit with sensitivity and noise performance comparable to recent designs, but with a reduced power requirement. CMRR improvement is achieved by subtracting differential inputs and superior noise performance compare to conventional structure, as amplifier noise and DAC kT/C noise is not amplified by triple-sampling structure while the signal is increased by its gain. Triple-sampling also can be operated as a single-to-differential circuit. A MEMS microphone incorporating this readout circuit, fabricated in a 0.18μm CMOS process, achieved an A-weighted SNR of 62.1 dBA at 94 dB SPL with 520 μA current consumption, to which triple-sampling was shown to contribute 4.5 dBA.CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.1.1 MEMS MICROPHONE TRENDS 1
1.1.2 TYPE OF MEMS MICROPHONES 4
1.1.3 PREVIOUS WORKS 7
1.2 MEMS MICROPHONE BASIC TERMS 9
1.3 THESIS ORGANIZATION 12
CHAPTER 2 SYSTEM OVERVIEW 13
2.1 SYSTEM ARCHITECTURE 13
CHAPTER 3 INTERFACE CIRCUITS AND POWER MANAGEMENT CIRCUITS 16
3.1 PSEUDO-DIFFERENTIAL SOURCE FOLLOWER 17
3.2 CHARGE PUMP 19
3.3 LOW DROPOUT REGULATOR 22
3.3.1 DESIGN CONSIDERATION OF LOW DROPOUT REGULATOR 22
3.3.2 IMPLEMENTATION OF LOW DROPOUT REGULATOR 26
CHAPTER 4 TRIPLE-SAMPLING DELTA-SIGMA ADC 31
4.1 BASIC OF DELTA-SIGMA ADC 31
4.2 IMPLEMENTATION OF TRIPLE-SAMPLING DELTA-SIGMA MODULATOR 37
4.2.1 CONVENTIONAL 1ST INTEGRATOR STRUCTURE 37
4.2.2 CROSS-SAMPLING 1ST INTEGRATOR 40
4.2.3 TRIPLE-SAMPLING 1ST INTEGRATOR 43
4.2.4 STF ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 47
4.2.5 THERMAL NOISE ANALYSIS OF TRIPLE-SAMPLING 1ST INTEGRATOR 51
4.2 CIRCUIT IMPLEMENTATION OF DELTA-SIGMA ADC 57
CHAPTER 5 MEASUREMENT RESULTS 64
5.1 MEASUREMENT ENVIRONMENT 64
5.2 MEASUREMENT RESULTS 67
5.3 PERFORMANCE SUMMARY 72
CHAPTER 6 CONCLUSION 74
BIBLIOGRAPHY 76
한글초록 79박
Implementation of a 4 Bit Direct Charge Transfer Switched Capacitor DAC and DWA DEM techniqueÂ
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Linear Precoding with Low-Resolution DACs for Massive MU-MIMO-OFDM Downlink
We consider the downlink of a massive multiuser (MU) multiple-input
multiple-output (MIMO) system in which the base station (BS) is equipped with
low-resolution digital-to-analog converters (DACs). In contrast to most
existing results, we assume that the system operates over a frequency-selective
wideband channel and uses orthogonal frequency division multiplexing (OFDM) to
simplify equalization at the user equipments (UEs). Furthermore, we consider
the practically relevant case of oversampling DACs. We theoretically analyze
the uncoded bit error rate (BER) performance with linear precoders (e.g., zero
forcing) and quadrature phase-shift keying using Bussgang's theorem. We also
develop a lower bound on the information-theoretic sum-rate throughput
achievable with Gaussian inputs, which can be evaluated in closed form for the
case of 1-bit DACs. For the case of multi-bit DACs, we derive approximate, yet
accurate, expressions for the distortion caused by low-precision DACs, which
can be used to establish lower bounds on the corresponding sum-rate throughput.
Our results demonstrate that, for a massive MU-MIMO-OFDM system with a
128-antenna BS serving 16 UEs, only 3--4 DAC bits are required to achieve an
uncoded BER of 10^-4 with a negligible performance loss compared to the
infinite-resolution case at the cost of additional out-of-band emissions.
Furthermore, our results highlight the importance of taking into account the
inherent spatial and temporal correlations caused by low-precision DACs
Low-pass CMOS Sigma-Delta Converter
A crescente necessidade em dar-se uma melhor saúde à população obriga ao desenvolvimento de novos e melhores dispositivos médicos. Atualmente, uma área de desenvolvimento importante é a de dispositivos portáteis para análise de sinais biológicos, tais como o eletrocardiograma ou o electroencefalograma, ajudando os profissionais de saúde a fazer rápidos diagnósticos no terreno, ou mesmo para serem usados por cidadãos que necessitem de vigilância constante.
O desenvolvimento destes aparelhos traz novos desafios para a comunidade cientifica, nomeadamente na interface analógico/digital, na qualidade dos dados obtidos e no gasto energético. Para se conceber um bom dispositivos médico é necessário um conversor analógico/digital para frequências baixas, com baixo consumo energético e elevada resolução.
Esta dissertação começa por fornecer ao leitor a teoria básica sobre conversores analógico/digital (ADC) e estado de arte. Como principal objetivo do trabalho desenvolvido, é descrito o desenho de um ADC baseado numa arquitetura Sigma-Delta que vá de encontro aos requisitos mencionados. O conversor foi implementado numa tecnologia 130 nm CMOS, usando uma frequência de amostragem de 1 MHz, com uma largura de banda de 1 kHz e tensão de alimentação 1,2 V. É usada, nos integradores do sigma-delta, uma invulgar tipologia de Opamp de forma a obter um ganho elevado, sem recurso a técnicas cascode. O quantizador possui uma resolução de 1,5 bits e é realizado com dois comparadores dinâmicos, de forma a minimizar o consumo energético.The growing need to provide better health for the population requires the development of new and better medical devices. Portable devices for the analysis of biological signals, such as the electrocardiogram or electroencephalogram, is nowadays an important development, helping health professionals to come up with fast diagnoses on the field, or even for use by citizens who require constant vigilance .
Developing these devices brings new challenges to the scientific community, namely at the analog/digital interface, the quality of data and power consumption. In order to design a good medical device it is necessary an analog/digital converter for low frequencies, with low power consumption and high resolution.
This dissertation begins by providing the reader with the basic theory of analog/digital (ADC) and its state of the art. The main goal of the work is the design of an ADC based on a Sigma-Delta architecture that meets the necessary medical requirements. The converter was implemented in a 130 nm CMOS technology using a sampling frequency of 1 MHz, with a bandwidth of 1 kHz, and a source voltage of 1.2 V. The integrators of sigma-delta employs an unusual Opamp typology in order to reach a high gain, without resourcing to cascode techniques. The quantizer has a resolution of 1.5 bits and is realized with two dynamic comparators, in order to minimize power consumption
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