Analog dithering techniques for highly linear and efficient transmitters

The current thesis is about investigation of new methods and techniques to be able to utilize the switched mode amplifiers, for linear and efficient applications. Switched mode amplifiers benefit from low overlap between the current and voltage wave forms in their output terminals, but they seriously suffer from nonlinearity. This makes it impossible to use them to amplify non-constant envelope message signals, where very high linearity is expected. In order to do that, dithering techniques are studied and a full linearity analysis approach is developed, by which the linearity performance of the dithered amplifier can be analyzed, based on the dithering level and frequency. The approach was based on orthogonalization of the equivalent nonlinearity and is capable of prediction of both co-channel and adjacent channel nonlinearity metrics, for a Gaussian complex or real input random signal. Behavioral switched mode amplifier models are studied and new models are developed, which can be utilized to predict the nonlinear performance of the dithered power amplifier, including the nonlinear capacitors effects. For HFD application, self-oscillating and asynchronous sigma delta techniques are currently used, as pulse with modulators (PWM), to encode a generic RF message signal, on the duty cycle of an output pulse train. The proposed models and analysis techniques were applied to this architecture in the first phase, and the method was validated with measurement on a prototype sample, realized in 65 nm TSMC CMOS technology. Afterwards, based on the same dithering phenomenon, a new linearization technique was proposed, which linearizes the switched mode class D amplifier, and at the same time can reduce the reactive power loss of the amplifier. This method is based on the dithering of the switched mode amplifier with frequencies lower than the band-pass message signal and is called low frequency dithering (LFD). To test this new technique, two test circuits were realized and the idea was applied to them. Both of the circuits were of the hard nonlinear type (class D) and are integrated CMOS and discrete LDMOS technologies respectively. The idea was successfully tested on both test circuits and all of the linearity metric predictions for a digitally modulated RF signal and a random signal were compared to the measurements. Moreover a search method to find the optimum dither frequency was proposed and validated. Finally, inspired by averaging interpretation of the dithering phenomenon, three new topologies were proposed, which are namely DLM, RF-ADC and area modulation power combining, which are all nonlinear systems linearized with dithering techniques. A new averaging method was developed and used for analysis of a Gilbert cell mixer topology, which resulted in a closed form relationship for the conversion gain, for long channel devices

High Efficiency Power Supplies for Multi-mode RF Power Amplifiers in Cellular Handset Applications

Cellular handset evolution requires the front end transmitter to support multiple 3G/4G bands for global roaming, and also to be backward compatible with the existing 2G (quad-band GSM/EDGE) network. The cost and size would be prohibitive if one power amplifier (PA) only supports one band or if multiple supplies are required for multiple PAs. Solutions of interest are based on multi-standard multi-band PAs (e.g. 2 multi-mode PAs instead of 8+ mode-specific PAs), and an efficient power supply that supports these multi-mode PAs. The thesis starts with a study of PA supply architectures and DC-DC converters. A series architecture consisting of a boost converter followed by a buck converter has advantages of low-noise buck converter output, together with the ability to deliver full power at low battery voltages to extend the battery life. The buck converter presents a constant power load for the boost converter, which raises stability concerns. Small-signal control-to-output transfer functions are derived for peak or valley current mode controlled boost converter with a downstream regulated converter modeled as constant power load. It is shown how current mode control provides active damping to ensure stability and well-behaved dynamic response. Furthermore, it is shown how load current feedforward presents an effective way to improve power load transient response. Modeling and design approaches are validated by test circuit simulations, demonstrating stable operations using current mode control under constant power loads, and improved power step load transient response based on load current feedforward. A buck/boost and LDO series architecture is proposed as the solution to address efficiency, linearity, noise and time mask requirements for the supplies supporting multi-standard, multi-band PAs. A monolithic integrated circuit (IC) has been designed and implemented in a standard 0.5 5V CMOS process for supplying the multi-mode PAs. The buck/boost converter with wide output range delivers the peak efficiency of 92%. The power LDO has 1-4 MHz bandwidth, to support the GSM/EDGE/WCDMA time mask requirements and the polar EDGE operation. The test chip consumes the quiescent current 1.1 mA, and it delivers maximum 5 W output

Low power VCO-based analog-to-digital conversion

textThis dissertation presents novel two stage ADC architecture with a VCO based second stage. With the scaling of the supply voltages in modern CMOS process it is difficult to design high gain operational amplifiers needed for traditional voltage domain two-stage analog to digital converters. However time resolution continues to improve with the advancement in CMOS technology making VCO-based ADC more attractive. The nonlinearity in voltage-to-frequency transfer function is the biggest challenge in design of VCO based ADC. The hybrid approach used in this work uses a voltage domain first stage to determine the most significant bits and uses a VCO based second stage to quantize the small residue obtained from first stage. The architecture relaxes the gain requirement on the the first stage opamp and also relaxes the linearity requirements on the second stage VCO. The prototype ADC built in 65nm CMOS process achieves 63.7dB SNDR in 10MHz bandwidth while only consuming 1.1mW of power. The performance of the prototype chip is comparable to the state-of-art in terms of figure-of-merit but this new architecture uses significantly less circuit area.Electrical and Computer Engineerin

Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier

The paper presents an original architecture andimplementation of 9-bit Linearized Pulse Width Modulator(LPWM) for Class-BD amplifier, based on the hybrid methodusing STM32 microcontroller and Programmable Tapped DelayLine (PTDL). The analog input signals are converted into 12-bitPCM signals, then are directly transformed into 32-bit LBDDDPWM data of the pulse-edge locations within n-th period of theswitching frequency, next requantized to the 9-bit digitaloutputs, and finally converted into the two physical trains of 1-bitPWM signals, to control the output stage of the Class-BD audioamplifier. The hybrid 9-bit quantizer converts 6 MSB bits usingcounter method, based on the peripherals of STM32microcontroller, while the remaining 3 LSB bits - using a methodbased on the PTDL. In the paper extensive verification ofalgorithm and circuit operation as well as simulation inMATLAB and experimental results of the proposed 9-bit hybridLBDD DPWM circuit have been performed. It allows to attainSNR of 80 dB and THD about 0,3% within the audio baseband

Analysis and design of ΣΔ Modulators for Radio Frequency Switchmode Power Amplifiers

Power amplifiers are an integral part of every basestation, macrocell, microcell and mobile phone, enabling data to be sent over the distances needed to reach the receiver’s antenna. While linear operation is needed for transmitting WCDMA and OFDM signals, linear operation of a power amplifier is characterized by low power efficiency, and contributes to unwanted power dissipation in a transmitter. Recently, a switchmode power amplifier operation was considered for reducing power losses in a RF transmitter. A linear and efficient operation of a PA can be achieved when the transmitted RF signal is ΣΔ modu- lated, and subsequently amplified by a nonlinear device. Although in theory this approach offers linearity and efficiency reaching 100%, the use of ΣΔ modulation for transmitting wideband signals causes problems in practical implementation: it requires high sampling rate by the digital hardware, which is needed for shaping large contents of a quantization noise induced by the modulator but also, the binary output from the modulator needs an RF power amplifier operating over very wide frequency band. This thesis addresses the problem of noise shaping in a ΣΔ modulator and nonlinear distortion caused by broadband operation in switchmode power amplifier driven by a ΣΔ modulated waveform. The problem of sampling rate increase in a ΣΔ modulator is solved by optimizing structure of the modulator, and subsequent processing of an input signal’s samples in parallel. Independent from the above, a novel technique for reducing quan- tization noise in a bandpass ΣΔ modulator using single bit quantizer is presented. The technique combines error pulse shaping and 3-level quantization for improving signal to noise ratio in a 2-level output. The improvement is achieved without the increase of a digital hardware’s sampling rate, which is advantageous also from the perspective of power consumption. The new method is explored in the course of analysis, and verified by simulated and experimental results. The process of RF signal conversion from the Cartesian to polar form is analyzed, and a signal modulator for a polar transmitter with a ΣΔ-digitized envelope signal is designed and implemented. The new modulator takes an advantage of bandpass digital to analog conversion for simplifying the analog part of the modulator. A deformation of the pulsed RF signal in the experimental modulator is demonstrated to have an effect primarily on amplitude of the RF signal, which is correctable with simple predistortion

Reduction of perceptual redundancy for data compression of television signals

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Receptores de rádio-frequência melhorados e disruptivos

This Ph.D. mainly addresses the reception part of a radio front end, focusing on Radio Frequency (RF) sampling architectures. These are considered to be the most promising future candidates to get better performance in terms of bandwidth and agility, following the well-known Software-Defined Radio (SDR) concept. The study considers the usage of an RF receiver in a standalone operation, i.e., used for receiving unknown data at the antenna, and when used as observation path for Power Amplifier (PA) linearization via Digital Predistortion (DPD), since nowadays this represents a mandatory technique to increase overall system’s performance. Firstly, commercial available RF Analog-Digital-Converters (ADCs) are studied and characterized to understand their limitations when used in DPD scenarios. A method for characterization and digital post-compensation to improve performance is proposed and evaluated. Secondly, an innovative FPGA-based RF single-bit pulsed converter based on Pulse Width Modulation (PWM) is addressed targeting frequency agility, high analog input bandwidth, and system integration, taking profit of an FPGA-based implementation. The latter was optimized based on PWM theoretical behavior maximizing Signal-to-Noise-Ratio (SNR) and bandwidth. The optimized receiver, was afterwards evaluated in a 5G C-RAN architecture and as a feedback loop for DPD. Finally, a brief study regarding DPD feedback loops in the scope of multiantenna transmitters is presented. This Ph.D. contributes with several advances to the state-of-the-art of SDR receiver, and to the so-called SDR DPD concept.Este doutoramento endereça principalmente a componente de receção de um transcetor de rádio-frequência (RF), focando-se em arquiteturas de receção de amostragem em RF. Estas são assim consideradas como sendo as mais promissoras para o futuro, em termos de desempenho, largura de banda e agilidade, de acordo com o conhecido conceito de Rádios Definidos por Software (SDR). O estudo considera o uso dos recetores de RF em modo standalone, i.e., recebendo dados desconhecidos provenientes da antena, e também quando usados como caminho de observação para aplicação de linearização de amplificadores de potência (PAs) via pré-distorção digital (DPD), pois atualmente esta é uma técnica fundamental para aumentar o desempenho geral do sistema. Em primeiro lugar, os conversores analógico-digital de RF são estudados e caracterizados para perceber as suas limitações quando usados em cenários de DPD. Um método de caracterização e pós compensação digital é proposto para obter melhorias de desempenho. Em segundo lugar, um novo recetor pulsado de um bit baseado em Modulação de Largura de Pulso (PWM) e implementado em Agregado de Células Lógicas Programáveis (FPGA) é endereçado, visando agilidade em frequência, largura de banda analógica e integração de sistema, tirando proveito da implementação em FPGA. Este recetor foi otimizado com base no modelo comportamental teórico da modulação PWM, maximizando a relação sinalruído (SNR) e a largura de banda. O recetor otimizado foi posteriormente avaliado num cenário 5G de uma arquitetura C-RAN e também num cenário em que serve de caminho de observação para DPD. Finalmente, um breve estudo relativo a caminhos de observação de DPD no contexto de transmissores multi-antena é também apresentado. Este doutoramento contribui com vários avanços no estado da arte de recetores SDR e no conceito de SDR DPD.Programa Doutoral em Engenharia Eletrotécnic

Digital Signal Processing Techniques Applied to Radio over Fiber Systems

The dissertation aims to analyze different Radio over Fiber systems for the front-haul applications. Particularly, analog radio over fiber (A-RoF) are simplest and suffer from nonlinearities, therefore, mitigating such nonlinearities through digital predistortion are studied. In particular for the long haul A-RoF links, direct digital predistortion technique (DPDT) is proposed which can be applied to reduce the impairments of A-RoF systems due to the combined effects of frequency chirp of the laser source and chromatic dispersion of the optical channel. Then, indirect learning architecture (ILA) based structures namely memory polynomial (MP), generalized memory polynomial (GMP) and decomposed vector rotation (DVR) models are employed to perform adaptive digital predistortion with low complexities. Distributed feedback (DFB) laser and vertical capacity surface emitting lasers (VCSELs) in combination with single mode/multi-mode fibers have been linearized with different quadrature amplitude modulation (QAM) formats for single and multichannel cases. Finally, a feedback adaptive DPD compensation is proposed. Then, there is still a possibility to exploit the other realizations of RoF namely digital radio over fiber (D-RoF) system where signal is digitized and transmits the digitized bit streams via digital optical communication links. The proposed solution is robust and immune to nonlinearities up-to 70 km of link length. Lastly, in light of disadvantages coming from A-RoF and D-RoF, it is still possible to take only the advantages from both methods and implement a more recent form knows as Sigma Delta Radio over Fiber (S-DRoF) system. Second Order Sigma Delta Modulator and Multi-stAge-noise-SHaping (MASH) based Sigma Delta Modulator are proposed. The workbench has been evaluated for 20 MHz LTE signal with 256 QAM modulation. Finally, The 6x2 GSa/s sigma delta modulators are realized on FPGA to show a real time demonstration of S-DRoF system. The demonstration shows that S-DRoF is a competitive competitor for 5G sub-6GHz band applications

High efficiency delta-sigma modulation data converters

Enabled by continued device scaling in CMOS technology, more and more functions that were previously realized in separate chips are getting integrated on a single chip nowadays. Integration on silicon has opened the door to new portable wireless applications, and initiated a widespread use of these devices in our common everyday life. Wide signal bandwidth, high linearity and dynamic range, and low power dissipation are required of embedded data converters that are the performance-limiting key building blocks of those systems. Thus, power-efficient and highly-linear data conversion over wide range of signal bands is essential to get the full benefits from device scaling. This continued trend keeps innovation in the design of data converter continuing. Traditionally, delta-sigma modulation data converters proved to be very effective in applications where high resolution was necessary in a relatively narrow signal band. There have been active research efforts across academia and industry on the extension of achievable signal bandwidth without compromising the performance of these data converters. In this dissertation, architectural innovations, combined with effective design techniques for delta-sigma modulation data converters, are presented to overcome the associated limitations. The effectiveness of the proposed approaches is demonstrated by test results for the following state-of-the-art prototype designs: (1) a 0.8 V, 2.6 mW, 88 dB dual-channel audio delta-sigma modulation D/A converter with headphone driver; (2) an 88 dB ring-coupled delta-sigma ADC with 1.9 MHz bandwidth and -102.4 dB THD; (3) a multi-cell noise-coupled delta-sigma ADC with 1.9 MHz bandwidth, 88 dB DR, and -98 dB THD; (4) an 8.1 mW, 82 dB self-coupled delta-sigma ADC with 1.9 MHz bandwidth and -97 dB THD; (5) a noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, -98 dB THD, and 79 dB SNDR; (6) a noise-coupled time-interleaved delta-sigma ADC with 2.5 MHz bandwidth, -104 dB THD, and 81 dB SNDR. As an extension of this research, two novel architectures for efficient double-sampling delta-sigma ADCs and improved low-distortion delta-sigma ADC are proposed, and validated by extensive simulations.Keywords: improved low-distortion modulator, time interleaving, data converter, multi-cell ADC, efficient double sampling, noise coupling, delta-sigma modulatio