Research on low power technology by AC power supply circuits

制度:新 ; 報告番号:甲3692号 ; 学位の種類:博士(工学) ; 授与年月日:2012/9/15 ; 早大学位記番号:新6060Waseda Universit

Design of Low Leakage Multi Threshold (Vth) CMOS Level Shifter

In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. MTCMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Leakage power dissipation has become an overriding concern for VLSI circuit designers. In this a “sleepy keeper” approach is preferred which reduces the leakage current while saving exact logic state. The new  low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. When the circuits are individually analyzed for power consumption at 45nm CMOS technology, the new level shifter offer significant power savings up to 37% as compared to the previous work. Alternatively, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with  our approach to the circuit. All the simulation results are based on 45nm CMOS technology and  simulated in cadence tool.DOI:http://dx.doi.org/10.11591/ijece.v3i5.316

Ultra-Low Power Circuit Design for Miniaturized IoT Platform

This thesis examines the ultra-low power circuit techniques for mm-scale Internet of Things (IoT) platforms. The IoT devices are known for their small form factors and limited battery capacity and lifespan. So, ultra-low power consumption of always-on blocks is required for the IoT devices that adopt aggressive duty-cycling for high power efficiency and long lifespan. Several problems need to be addressed regarding IoT device designs, such as ultra-low power circuit design techniques for sleep mode and energy-efficient and fast data rate transmission for active mode communication. Therefore, this thesis highlights the ultra-low power always-on systems, focusing on energy efficient optical transmission in order to miniaturize the IoT systems. First, this thesis presents a battery-less sub-nW micro-controller for an always-operating system implemented with a newly proposed logic family. Second, it proposes an always-operating sub-nW light-to-digital converter to measure instant light intensity and cumulative light exposure, which employs the characteristics of this proposed logic family. Third, it presents an ultra-low standby power optical wake-up receiver with ambient light canceling using dual-mode operation. Finally, an energy-efficient low power optical transmitter for an implantable IoT device is suggested. Implications for future research are also provided.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/145862/1/imhotep_1.pd

Design, analysis and implementation of voltage sensor for power-constrained systems

PhD ThesisThanks to an extensive effort by the global research community, the electronic technology has significantly matured over the last decade. This technology has enabled certain operations which humans could not otherwise easily perform. For instance, electronic systems can be used to perform sensing, monitoring and even control operations in environments such as outer space, underground, under the sea or even inside the human body. The main difficulty for electronics operating in these environments is access to a reliable and permanent source of energy. Using batteries as the immediate solution for this problem has helped to provide energy for limited periods of time; however, regular maintenance and replacement are required. Consequently, battery solutions fail wherever replacing them is not possible or operation for long periods is needed. For such cases, researchers have proposed harvesting ambient energy and converting it into an electrical form. An important issue with energy harvesters is that their operation and output power depend critically on the amount of energy they receive and because ambient energy often tends to be sporadic in nature, energy harvesters cannot produce stable or fixed levels of power all of the time. Therefore, electronic devices powered in this way must be capable of adapting their operation to the energy status of the harvester. To achieve this, information on the energy available for use is needed. This can be provided by a sensor capable of measuring voltage. However, stable and fixed voltage and time references are a prerequisite of most traditional voltage measurement devices, but these generally do not exist in energy harvesting environments. A further challenge is that such a sensor also needs to be powered by the energy harvester’s unstable voltage. In this thesis, the design of a reference-free voltage sensor, which can operate with a varying voltage source, is provided based on the capture of a portion of the total energy which is directly related to II the energy being sensed. This energy is then used to power a computation which quantifies captured energy over time, with the information directly generated as digital code. The sensor was fabricated in the 180 nm technology node and successfully tested by performing voltage measurements over the range 1.8 V to 0.8 V

Reliability and security in low power circuits and systems

With the massive deployment of mobile devices in sensitive areas such as healthcare and defense, hardware reliability and security have become hot research topics in recent years. These topics, although different in definition, are usually correlated. This dissertation offers an in-depth treatment on enhancing the reliability and security of low power circuits and systems. The first part of the dissertation deals with the reliability of sub-threshold designs, which use supply voltage lower than the threshold voltage (Vth) of transistors to reduce power. The exponential relationship between delay and Vth significantly jeopardizes their reliability due to process variation induced timing violations. In order to address this problem, this dissertation proposes a novel selective body biasing scheme. In the first work, the selective body biasing problem is formulated as a linearly constrained statistical optimization model, and the adaptive filtering concept is borrowed from the signal processing community to develop an efficient solution. However, since the adaptive filtering algorithm lacks theoretical justification and guaranteed convergence rate, in the second work, a new approach based on semi-infinite programming with incremental hypercubic sampling is proposed, which demonstrates better solution quality with shorter runtime. The second work deals with the security of low power crypto-processors, equipped with Random Dynamic Voltage Scaling (RDVS), in the presence of Correlation Power Analysis (CPA) attacks. This dissertation firstly demonstrates that the resistance of RDVS to CPA can be undermined by lowering power supply voltage. Then, an alarm circuit is proposed to resist this attack. However, the alarm circuit will lead to potential denial-of-service due to noise-triggered false alarms. A non-zero sum game model is then formulated and the Nash Equilibria is analyzed --Abstract, page iii

RF Power Transfer, Energy Harvesting, and Power Management Strategies

Energy harvesting is the way to capture green energy. This can be thought of as a recycling process where energy is converted from one form (here, non-electrical) to another (here, electrical). This is done on the large energy scale as well as low energy scale. The former can enable sustainable operation of facilities, while the latter can have a significant impact on the problems of energy constrained portable applications. Different energy sources can be complementary to one another and combining multiple-source is of great importance. In particular, RF energy harvesting is a natural choice for the portable applications. There are many advantages, such as cordless operation and light-weight. Moreover, the needed infra-structure can possibly be incorporated with wearable and portable devices. RF energy harvesting is an enabling key player for Internet of Things technology. The RF energy harvesting systems consist of external antennas, LC matching networks, RF rectifiers for ac to dc conversion, and sometimes power management. Moreover, combining different energy harvesting sources is essential for robustness and sustainability. Wireless power transfer has recently been applied for battery charging of portable devices. This charging process impacts the daily experience of every human who uses electronic applications. Instead of having many types of cumbersome cords and many different standards while the users are responsible to connect periodically to ac outlets, the new approach is to have the transmitters ready in the near region and can transfer power wirelessly to the devices whenever needed. Wireless power transfer consists of a dc to ac conversion transmitter, coupled inductors between transmitter and receiver, and an ac to dc conversion receiver. Alternative far field operation is still tested for health issues. So, the focus in this study is on near field. The goals of this study are to investigate the possibilities of RF energy harvesting from various sources in the far field, dc energy combining, wireless power transfer in the near field, the underlying power management strategies, and the integration on silicon. This integration is the ultimate goal for cheap solutions to enable the technology for broader use. All systems were designed, implemented and tested to demonstrate proof-of concept prototypes

In Situ Automatic Analog Circuit Calibration and Optimization

As semiconductor technology scales down, the variations of active/passive device characteristics after fabrication are getting more and more significant. As a result, many circuits need more accuracy margin to meet minimum accuracy specifications over huge process-voltage-temperature (PVT) variations. Although, overdesigning a circuit is sometimes not a feasible option because of excessive accuracy margin that requires high power consumption and large area. Consequently, calibration/tuning circuits that can automatically detect and compensate the variations have been researched for analog circuits to make better trade-offs among accuracy, power consumption, and area. The first part of this dissertation shows that a newly proposed in situ calibration circuit for a current reference can relax the sharp trade-off between the temperature coefficient accuracy and the power consumption of the current reference. Prototype chips fabricated in a 180 nm CMOS technology generate 1 nA and achieve an average temperature coefficient of 289 ppm/°C and an average line sensitivity of 1.4 %/V with no help from a multiple-temperature trimming. Compared with other state-of-the-art current references that do not need a multiple-temperature trimming, the proposed circuit consumes at least 74% less power, while maintaining similar or higher accuracy. The second part of this dissertation proves that a newly proposed multidimensional in situ analog circuit optimization platform can optimize a Tow-Thomas bandpass biquad. Unlike conventional calibration/tuning approaches, which only handle one or two frequency-domain characteristics, the proposed platform optimizes the power consumption, frequency-, and time-domain characteristics of the biquad to make a better trade-off between the accuracy and the power consumption of the biquad. Simulation results show that this platform reduces the gain-bandwidth product of op-amps in the biquad by 80% while reducing the standard deviations of frequency- and time-domain characteristics by 82%. Measurement results of a prototype chip fabricated in a 180 nm CMOS technology also show that this platform can save maximum 71% of the power consumption of the biquad while the biquad maintains its frequency-domain characteristics: Q, ωO and the gain at ωO

Dual-frequency single-inductor multiple-output (DF-SIMO) power converter topology for SoC applications

Modern mixed-signal SoCs integrate a large number of sub-systems in a single nanometer CMOS chip. Each sub-system typically requires its own independent and well-isolated power supply. However, to build these power supplies requires many large off-chip passive components, and thus the bill of material, the package pin count, and the printed circuit board area and complexity increase dramatically, leading to higher overall cost. Conventional (single-frequency) Single-Inductor Multiple-Output (SIMO) power converter topology can be employed to reduce the burden of off-chip inductors while producing a large number of outputs. However, this strategy requires even larger off-chip output capacitors than single-output converters due to time multiplexing between the multiple outputs, and thus many of them suffer from cross coupling issues that limit the isolation between the outputs. In this thesis, a Dual-Frequency SIMO (DF-SIMO) buck converter topology is proposed. Unlike conventional SIMO topologies, the DF-SIMO decouples the rate of power conversion at the input stage from the rate of power distribution at the output stage. Switching the input stage at low frequency (~2 MHz) simplifies its design in nanometer CMOS, especially with input voltages higher than 1.2 V, while switching the output stage at higher frequency enables faster output dynamic response, better cross-regulation, and smaller output capacitors without the efficiency and design complexity penalty of switching both the input and output stages at high frequency. Moreover, for output switching frequency higher than 100 MHz, the output capacitors can be small enough to be integrated on-chip. A 5-output 2-MHz/120-MHz design in 45-nm CMOS with 1.8-V input targeting low-power microcontrollers is presented as an application. The outputs vary from 0.6 to 1.6 V, with 4 outputs providing up to 15 mA and one output providing up to 50 mA. The design uses single 10-uH off-chip inductor, 2-nF on-chip capacitor for each 15-mA output and 4.5-nF for the 50-mA output. The peak efficiency is 73%, Dynamic Voltage Scaling (DVS) is 0.6 V/80 ns, and settling time is 30 ns for half-to-full load steps with no observable overshoot/undershoot or cross-coupling transients. The DF-SIMO topology enables realizing multiple efficient power supplies with faster dynamic response, better cross-regulation, and lower overall cost compared to conventional SIMO topologies