Near-capacity MIMOs using iterative detection

In this thesis, Multiple-Input Multiple-Output (MIMO) techniques designed for transmission over narrowband Rayleigh fading channels are investigated. Specifically, in order to providea diversity gain while eliminating the complexity of MIMO channel estimation, a Differential Space-Time Spreading (DSTS) scheme is designed that employs non-coherent detection. Additionally, in order to maximise the coding advantage of DSTS, it is combined with Sphere Packing (SP) modulation. The related capacity analysis shows that the DSTS-SP scheme exhibits a higher capacity than its counterpart dispensing with SP. Furthermore, in order to attain additional performance gains, the DSTS system invokes iterative detection, where the outer code is constituted by a Recursive Systematic Convolutional (RSC) code, while the inner code is a SP demapper in one of the prototype systems investigated, while the other scheme employs a Unity Rate Code (URC) as its inner code in order to eliminate the error floor exhibited by the system dispensing with URC. EXIT charts are used to analyse the convergence behaviour of the iteratively detected schemes and a novel technique is proposed for computing the maximum achievable rate of the system based on EXIT charts. Explicitly, the four-antenna-aided DSTSSP system employing no URC precoding attains a coding gain of 12 dB at a BER of 10-5 and performs within 1.82 dB from the maximum achievable rate limit. By contrast, the URC aidedprecoded system operates within 0.92 dB from the same limit.On the other hand, in order to maximise the DSTS system’s throughput, an adaptive DSTSSP scheme is proposed that exploits the advantages of differential encoding, iterative decoding as well as SP modulation. The achievable integrity and bit rate enhancements of the system are determined by the following factors: the specific MIMO configuration used for transmitting data from the four antennas, the spreading factor used and the RSC encoder’s code rate.Additionally, multi-functional MIMO techniques are designed to provide diversity gains, multiplexing gains and beamforming gains by combining the benefits of space-time codes, VBLASTand beamforming. First, a system employing Nt=4 transmit Antenna Arrays (AA) with LAA number of elements per AA and Nr=4 receive antennas is proposed, which is referred to as a Layered Steered Space-Time Code (LSSTC). Three iteratively detected near-capacity LSSTC-SP receiver structures are proposed, which differ in the number of inner iterations employed between the inner decoder and the SP demapper as well as in the choice of the outer code, which is either an RSC code or an Irregular Convolutional Code (IrCC). The three systems are capable of operating within 0.9, 0.4 and 0.6 dB from the maximum achievable rate limit of the system. A comparison between the three iteratively-detected schemes reveals that a carefully designed two-stage iterative detection scheme is capable of operating sufficiently close to capacity at a lower complexity, when compared to a three-stage system employing a RSC or a two-stage system using an IrCC as an outer code. On the other hand, in order to allow the LSSTC scheme to employ less receive antennas than transmit antennas, while still accommodating multiple users, a Layered Steered Space-Time Spreading (LSSTS) scheme is proposed that combines the benefits of space-time spreading, V-BLAST, beamforming and generalised MC DS-CDMA. Furthermore, iteratively detected LSSTS schemes are presented and an LLR post-processing technique is proposed in order to improve the attainable performance of the iteratively detected LSSTS system.Finally, a distributed turbo coding scheme is proposed that combines the benefits of turbo coding and cooperative communication, where iterative detection is employed by exchanging extrinsic information between the decoders of different single-antenna-aided users. Specifically, the effect of the errors induced in the first phase of cooperation, where the two users exchange their data, on the performance of the uplink in studied, while considering different fading channel characteristics

Signal design for Multiple-Antenna Systems and Wireless Networks

This dissertation is concerned with the signal design problems for Multiple Input and Multiple Output (MIMO) antenna systems and wireless networks. Three related but distinct problems are considered.The first problem considered is the design of space time codes for MIMO systems in the case when neither the transmitter nor the receiver knows the channel. We present the theoretical concept of communicating over block fading channel using Layered Unitary Space Time Codes (LUSTC), where the input signal is formed as a product of a series of unitary matrices with corresponding dimensionality. We show the channel capacity using isotropically distributed (i.d.) input signaling and optimal decoding can be achieved by layered i.d. signaling scheme along with a low complexity successive decoding. The closed form layered channel capacity is obtained, which serves as a design guideline for practical LUSTC. In the design of LUSTC, a successive design method is applied to leverage the problem of optimizing over lots of parameters.The feedback of channel state information (CSI) to the transmitter in MIMO systems is known to increase the forward channel capacity. A suboptimal power allocation scheme for MIMO systems is then proposed for limited rate feedback of CSI. We find that the capacity loss of this simple scheme is rather small compared to the optimal water-filling solution. This knowledge is applied for the design of the feedback codebook. In the codebook design, a generalized Lloyd algorithm is employed, in which the computation of the centroid is formulated as an optimization problem and solved optimally. Numerical results show that the proposed codebook design outperforms the existing algorithms in the literature.While it is not feasible to deploy multiple antennas in a wireless node due to the space limitation, user cooperation is an alternative to increase performance of the wireless networks. To this end, a coded user cooperation scheme is considered in the dissertation, which is shown to be equivalent to a coding scheme with the encoding done in a distributive manner. Utilizing the coding theoretic bound and simulation results, we show that the coded user cooperation scheme has great advantage over the non-cooperative scheme

VLSI algorithms and architectures for non-binary-LDPC decoding

Tesis por compendio[EN] This thesis studies the design of low-complexity soft-decision Non-Binary Low-Density Parity-Check (NB-LDPC) decoding algorithms and their corresponding hardware architectures suitable for decoding high-rate codes at high throughput (hundreds of Mbps and Gbps). In the first part of the thesis the main aspects concerning to the NB-LDPC codes are analyzed, including a study of the main bottlenecks of conventional softdecision decoding algorithms (Q-ary Sum of Products (QSPA), Extended Min-Sum (EMS), Min-Max and Trellis-Extended Min-Sum (T-EMS)) and their corresponding hardware architectures. Despite the limitations of T-EMS algorithm (high complexity in the Check Node (CN) processor, wiring congestion due to the high number of exchanged messages between processors and the inability to implement decoders over high-order Galois fields due to the high decoder complexity), it was selected as starting point for this thesis due to its capability to reach high-throughput. Taking into account the identified limitations of the T-EMS algorithm, the second part of the thesis includes six papers with the results of the research made in order to mitigate the T-EMS disadvantages, offering solutions that reduce the area, the latency and increase the throughput compared to previous proposals from literature without sacrificing coding gain. Specifically, five low-complexity decoding algorithms are proposed, which introduce simplifications in different parts of the decoding process. Besides, five complete decoder architectures are designed and implemented on a 90nm Complementary Metal-Oxide-Semiconductor (CMOS) technology. The results show an achievement in throughput higher than 1Gbps and an area less than 10 mm2. The increase in throughput is 120% and the reduction in area is 53% compared to previous implementations of T-EMS, for the (837,726) NB-LDPC code over GF(32). The proposed decoders reduce the CN area, latency, wiring between CN and Variable Node (VN) processor and the number of storage elements required in the decoder. Considering that these proposals improve both area and speed, the efficiency parameter (Mbps / Million NAND gates) is increased in almost five times compared to other proposals from literature. The improvements in terms of area allow us to implement NB-LDPC decoders over high-order fields which had not been possible until now due to the highcomplexity of decoders previously proposed in literature. Therefore, we present the first post-place and route report for high-rate codes over high-order fields higher than Galois Field (GF)(32). For example, for the (1536,1344) NB-LDPC code over GF(64) the throughput is 1259Mbps occupying an area of 28.90 mm2. On the other hand, a decoder architecture is implemented on a Field Programmable Gate Array (FPGA) device achieving 630 Mbps for the high-rate (2304,2048) NB-LDPC code over GF(16). To the best knowledge of the author, these results constitute the highest ones presented in literature for similar codes and implemented on the same technologies.[ES] En esta tesis se aborda el estudio del diseño de algoritmos de baja complejidad para la decodificación de códigos de comprobación de paridad de baja densidad no binarios (NB-LDPC) y sus correspondientes arquitecturas apropiadas para decodificar códigos de alta tasa a altas velocidades (cientos de Mbps y Gbps). En la primera parte de la tesis los principales aspectos concernientes a los códigos NB-LDPC son analizados, incluyendo un estudio de los principales cuellos de botella presentes en los algoritmos de decodificación convencionales basados en decisión blanda (QSPA, EMS, Min-Max y T-EMS) y sus correspondientes arquitecturas hardware. A pesar de las limitaciones del algoritmo T-EMS (alta complejidad en el procesador del nodo de chequeo de paridad (CN), congestión en el rutado debido al intercambio de mensajes entre procesadores y la incapacidad de implementar decodificadores para campos de Galois de orden elevado debido a la elevada complejidad), éste fue seleccionado como punto de partida para esta tesis debido a su capacidad para alcanzar altas velocidades. Tomando en cuenta las limitaciones identificadas en el algoritmo T-EMS, la segunda parte de la tesis incluye seis artículos con los resultados de la investigación realizada con la finalidad de mitigar las desventajas del algoritmo T-EMS, ofreciendo soluciones que reducen el área, la latencia e incrementando la velocidad comparado con propuestas previas de la literatura sin sacrificar la ganancia de codificación. Especificamente, cinco algoritmos de decodificación de baja complejidad han sido propuestos, introduciendo simplificaciones en diferentes partes del proceso de decodificación. Además, arquitecturas completas de decodificadores han sido diseñadas e implementadas en una tecnologia CMOS de 90nm consiguiéndose una velocidad mayor a 1Gbps con un área menor a 10 mm2, aumentando la velocidad en 120% y reduciendo el área en 53% comparado con previas implementaciones del algoritmo T-EMS para el código (837,726) implementado sobre campo de Galois GF(32). Las arquitecturas propuestas reducen el área del CN, latencia, número de mensajes intercambiados entre el nodo de comprobación de paridad (CN) y el nodo variable (VN) y el número de elementos de almacenamiento en el decodificador. Considerando que estas propuestas mejoran tanto el área comola velocidad, el parámetro de eficiencia (Mbps / Millones de puertas NAND) se ha incrementado en casi cinco veces comparado con otras propuestas de la literatura. Las mejoras en términos de área nos ha permitido implementar decodificadores NBLDPC sobre campos de Galois de orden elevado, lo cual no habia sido posible hasta ahora debido a la alta complejidad de los decodificadores anteriormente propuestos en la literatura. Por lo tanto, en esta tesis se presentan los primeros resultados incluyendo el emplazamiento y rutado para códigos de alta tasa sobre campos finitos de orden mayor a GF(32). Por ejemplo, para el código (1536,1344) sobre GF(64) la velocidad es 1259 Mbps ocupando un área de 28.90 mm2. Por otro lado, una arquitectura de decodificador ha sido implementada en un dispositivo FPGA consiguiendo 660 Mbps de velocidad para el código de alta tasa (2304,2048) sobre GF(16). Estos resultados constituyen, según el mejor conocimiento del autor, los mayores presentados en la literatura para códigos similares implementados para las mismas tecnologías.[CA] En esta tesi s'aborda l'estudi del disseny d'algoritmes de baixa complexitat per a la descodificació de codis de comprovació de paritat de baixa densitat no binaris (NB-LDPC), i les seues corresponents arquitectures per a descodificar codis d'alta taxa a altes velocitats (centenars de Mbps i Gbps). En la primera part de la tesi els principals aspectes concernent als codis NBLDPC són analitzats, incloent un estudi dels principals colls de botella presents en els algoritmes de descodificació convencionals basats en decisió blana (QSPA, EMS, Min-Max i T-EMS) i les seues corresponents arquitectures. A pesar de les limitacions de l'algoritme T-EMS (alta complexitat en el processador del node de revisió de paritat (CN), congestió en el rutat a causa de l'intercanvi de missatges entre processadors i la incapacitat d'implementar descodificadors per a camps de Galois d'orde elevat a causa de l'elevada complexitat), este va ser seleccionat com a punt de partida per a esta tesi degut a la seua capacitat per a aconseguir altes velocitats. Tenint en compte les limitacions identificades en l'algoritme T-EMS, la segona part de la tesi inclou sis articles amb els resultats de la investigació realitzada amb la finalitat de mitigar els desavantatges de l'algoritme T-EMS, oferint solucions que redueixen l'àrea, la latència i incrementant la velocitat comparat amb propostes prèvies de la literatura sense sacrificar el guany de codificació. Específicament, s'han proposat cinc algoritmes de descodificació de baixa complexitat, introduint simplificacions en diferents parts del procés de descodificació. A més, s'han dissenyat arquitectures completes de descodificadors i s'han implementat en una tecnologia CMOS de 90nm aconseguint-se una velocitat major a 1Gbps amb una àrea menor a 10 mm2, augmentant la velocitat en 120% i reduint l'àrea en 53% comparat amb prèvies implementacions de l'algoritme T-EMS per al codi (837,726) implementat sobre camp de Galois GF(32). Les arquitectures proposades redueixen l'àrea del CN, la latència, el nombre de missatges intercanviats entre el node de comprovació de paritat (CN) i el node variable (VN) i el nombre d'elements d'emmagatzemament en el descodificador. Considerant que estes propostes milloren tant l'àrea com la velocitat, el paràmetre d'eficiència (Mbps / Milions deportes NAND) s'ha incrementat en quasi cinc vegades comparat amb altres propostes de la literatura. Les millores en termes d'àrea ens ha permès implementar descodificadors NBLDPC sobre camps de Galois d'orde elevat, la qual cosa no havia sigut possible fins ara a causa de l'alta complexitat dels descodificadors anteriorment proposats en la literatura. Per tant, nosaltres presentem els primers reports després de l'emplaçament i rutat per a codis d'alta taxa sobre camps finits d'orde major a GF(32). Per exemple, per al codi (1536,1344) sobre GF(64) la velocitat és 1259 Mbps ocupant una àrea de 28.90 mm2. D'altra banda, una arquitectura de descodificador ha sigut implementada en un dispositiu FPGA aconseguint 660 Mbps de velocitat per al codi d'alta taxa (2304,2048) sobre GF(16). Estos resultats constitueixen, per al millor coneixement de l'autor, els millors presentats en la literatura per a codis semblants implementats per a les mateixes tecnologies.Lacruz Jucht, JO. (2016). VLSI algorithms and architectures for non-binary-LDPC decoding [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/73266TESISCompendi

A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation

5G New Radio (NR) has stringent demands on both performance and complexity for the design of low-density parity-check (LDPC) decoding algorithms and corresponding VLSI implementations. Furthermore, decoders must fully support the wide range of all 5G NR blocklengths and code rates, which is a significant challenge. In this paper, we present a high-performance and low-complexity LDPC decoder, tailor-made to fulfill the 5G requirements. First, to close the gap between belief propagation (BP) decoding and its approximations in hardware, we propose an extension of adjusted min-sum decoding, called generalized adjusted min-sum (GA-MS) decoding. This decoding algorithm flexibly truncates the incoming messages at the check node level and carefully approximates the non-linear functions of BP decoding to balance the error-rate and hardware complexity. Numerical results demonstrate that the proposed fixed-point GAMS has only a minor gap of 0.1 dB compared to floating-point BP under various scenarios of 5G standard specifications. Secondly, we present a fully reconfigurable 5G NR LDPC decoder implementation based on GA-MS decoding. Given that memory occupies a substantial portion of the decoder area, we adopt multiple data compression and approximation techniques to reduce 42.2% of the memory overhead. The corresponding 28nm FD-SOI ASIC decoder has a core area of 1.823 mm2 and operates at 895 MHz. It is compatible with all 5G NR LDPC codes and achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of 13.40 Gbps/mm2 at 4 decoding iterations.Comment: 14 pages, 14 figure

Estimation and detection techniques for doubly-selective channels in wireless communications

A fundamental problem in communications is the estimation of the channel. The signal transmitted through a communications channel undergoes distortions so that it is often received in an unrecognizable form at the receiver. The receiver must expend significant signal processing effort in order to be able to decode the transmit signal from this received signal. This signal processing requires knowledge of how the channel distorts the transmit signal, i.e. channel knowledge. To maintain a reliable link, the channel must be estimated and tracked by the receiver. The estimation of the channel at the receiver often proceeds by transmission of a signal called the 'pilot' which is known a priori to the receiver. The receiver forms its estimate of the transmitted signal based on how this known signal is distorted by the channel, i.e. it estimates the channel from the received signal and the pilot. This design of the pilot is a function of the modulation, the type of training and the channel. [Continues.