Efficient and multiplierless design of FIR filters with very sharp cutoff via maximally flat building blocks

A new design technique for linear-phase FIR filters, based on maximally flat buildiing blocks, is presented. The design technique does not involve iterative approximations and is, therefore, fast. It gives rise to filters that have a monotone stopband response, as required in some applications. The technique is partially based on an interpolative scheme. Implementation of the obtained filter designs requires a much smaller number of multiplications than maximally flat (MAXFLAT) FIR filters designed by the conventional approach. A technique based on FIR spectral transformations to design new multiplierless FIR filter structures is then advanced, and multiplierless implementations for sharp cutoff specifications are included

Efficient and multiplierless design of FIR filters with very sharp cutoff via maximally flat building blocks

A new design technique for linear-phase FIR filters, based on maximally flat buildiing blocks, is presented. The design technique does not involve iterative approximations and is, therefore, fast. It gives rise to filters that have a monotone stopband response, as required in some applications. The technique is partially based on an interpolative scheme. Implementation of the obtained filter designs requires a much smaller number of multiplications than maximally flat (MAXFLAT) FIR filters designed by the conventional approach. A technique based on FIR spectral transformations to design new multiplierless FIR filter structures is then advanced, and multiplierless implementations for sharp cutoff specifications are included

Multiplierless CSD techniques for high performance FPGA implementation of digital filters.

I leverage FastCSD to develop a new, high performance iterative multiplierless structure based on a novel real-time CSD recoding, so that more zero partial products are introduced. Up to 66.7% zero partial products occur compared to 50% in the traditional modified Booth's recoding. Also, this structure reduces the non-zero partial products to a minimum. As a result, the number of arithmetic operations in the carry-save structure is reduced. Thus, an overall speed-up, as well as low-power consumption can be achieved. Furthermore, because the proposed structure involves real time CSD recoding and does not require a fixed value for the multiplier input to be known a priori, the proposed multiplier can be applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters.My work is based on a dramatic new technique for converting between 2's complement and CSD number systems, and results in high-performance structures that are particularly effective for implementing adaptive systems in reconfigurable logic.My research focus is on two key ideas for improving DSP performance: (1) Develop new high performance, efficient shift-add techniques ("multiplierless") to implement the multiply-add operations without the need for a traditional multiplier structure. (2) There is a growing trend toward design prototyping and even production in FPGAs as opposed to dedicated DSP processors or ASICs; leverage this trend synergistically with the new multiplierless structures to improve performance.Implementation of digital signal processing (DSP) algorithms in hardware, such as field programmable gate arrays (FPGAs), requires a large number of multipliers. Fast, low area multiply-adds have become critical in modern commercial and military DSP applications. In many contemporary real-time DSP and multimedia applications, system performance is severely impacted by the limitations of currently available speed, energy efficiency, and area requirement of an onboard silicon multiplier.I also introduce a new multi-input Canonical Signed Digit (CSD) multiplier unit, which requires fewer shift/add/subtract operations and reduced CSD number conversion overhead compared to existing techniques. This results in reduced power consumption and area requirements in the hardware implementation of DSP algorithms. Furthermore, because all the products are produced simultaneously, the multiplication speed and thus the throughput are improved. The multi-input multiplier unit is applied to implement digital filters with non-fixed filter coefficients, such as adaptive filters. The implementation cost of these digital filters can be further reduced by limiting the wordlength of the input signal with little or no sacrifice to the filter performance, which is confirmed by my simulation results. The proposed multiplier unit can also be applied to other DSP algorithms, such as digital filter banks or matrix and vector multiplications.Finally, the tradeoff between filter order and coefficient length in the design and implementation of high-performance filters in Field Programmable Gate Arrays (FPGAs) is discussed. Non-minimum order FIR filters are designed for implementation using Canonical Signed Digit (CSD) multiplierless implementation techniques. By increasing the filter order, the length of the coefficients can be decreased without reducing the filter performance. Thus, an overall hardware savings can be achieved.Adaptive system implementations require real-time conversion of coefficients to Canonical Signed Digit (CSD) or similar representations to benefit from multiplierless techniques for implementing filters. Multiplierless approaches are used to reduce the hardware and increase the throughput. This dissertation introduces the first non-iterative hardware algorithm to convert 2's complement numbers to their CSD representations (FastCSD) using a fixed number of shift and logic operations. As a result, the power consumption and area requirements required for hardware implementation of DSP algorithms in which the coefficients are not known a priori can be greatly reduced. Because all CSD digits are produced simultaneously, the conversion speed and thus the throughput are improved when compared to overlap-and-scan techniques such as Booth's recoding

On the design and multiplierless realization of perfect reconstruction triplet-based FIR filter banks and wavelet bases

This paper proposes new methods for the efficient design and realization of perfect reconstruction (PR) two-channel finite-impulse response (FIR) triplet filter banks (FBs) and wavelet bases. It extends the linear-phase FIR triplet FBs of Ansari et al. to include FIR triplet FBs with lower system delay and a prescribed order of K regularity. The design problem using either the minimax error or least-squares criteria is formulated as a semidefinite programming problem, which is a very flexible framework to incorporate linear and convex quadratic constraints. The K regularity conditions are also expressed as a set of linear equality constraints in the variables to be optimized and they are structurally imposed into the design problem by eliminating the redundant variables. The design method is applicable to linear-phase as well as low-delay triplet FBs. Design examples are given to demonstrate the effectiveness of the proposed method. Furthermore, it was found that the analysis and synthesis filters of the triplet FB have a more symmetric frequency responses. This property is exploited to construct a class of PR M-channel uniform FBs and wavelets with M = 2 L, where L is a positive integer, using a particular tree structure. The filter lengths of the two-channel FBs down the tree are approximately reduced by a factor of two at each level or stage, while the transition bandwidths are successively increased by the same factor. Because of the downsampling operations, the frequency responses of the final analysis filters closely resemble those in a uniform FB with identical transition bandwidth. This triplet-based uniform M-channel FB has very low design complexity and the PR condition and K regularity conditions are structurally imposed. Furthermore, it has considerably lower arithmetic complexity and system delay than conventional tree structure using identical FB at all levels. The multiplierless realization of these FBs using sum-of-power-of-two (SOPOT) coefficients and multiplier block is also studied. © 2004 IEEE.published_or_final_versio

High throughput spatial convolution filters on FPGAs

Digital signal processing (DSP) on field- programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30–60 FPS, while maintaining functional flexibility

Design and multiplierless realization of digital synthesis filters for hybrid-filter-bank A/D converters

This paper studies the optimal least squares and minimax design and realization of digital synthesis filters for hybrid-filter-bank analog-to-digltal converters (HFB ADCs) to meet a given spurious-free dynamic range (SFDR). The problem for designing finite-impulse-response synthesis filters is formulated as a second-order cone-programming problem, which is convex and allows linear and quadratic constraints such as peak aliasing error to be incorporated. The fixed coefficients of the designed synthesis filters are efficiently implemented using sum-of-power-of-two (SOPOT) coefficients, while the internal word length used for each intermediate data is minimized using geometric programming. The main sources of error are analyzed, and a new formula of SFDR in terms of these errors is derived. The effects of component variations of analog analysis filters on the HFB ADC are also addressed by means of two new robust HFB ADC design algorithms based on stochastic uncertainty and worst case uncertainty models. Design results show that the proposed approach offers more flexibility and better performance than conventional methods in achieving a given SFDR and that the robust design algorithms are more robust to parameter uncertainties than the nominal design in which the uncertainties are not taken into account. © 2009 IEEE.published_or_final_versio

Design and multiplier-less implementation of a class of two-channel PR FIR filterbanks and wavelets with low system delay

In this paper, a new method for designing two-channel PR FIR filterbanks with low system delay is proposed. It is based on the generalization of the structure previously proposed by Phoong et al. Such structurally PR filterbanks are parameterized by two functions (β(z) and α(z)) that can be chosen as linear-phase FIR or allpass functions to construct FIR/IIR filterbanks with good frequency characteristics. The case of using identical β(z) and α(z) was considered by Phoong et al. with the delay parameter M chosen as 2N - 1. In this paper, the more general case of using different nonlinear-phase FIR functions for β(z) and α(z) is studied. As the linear-phase constraint is relaxed, the lengths of β(z) and α(z) are no longer restricted by the delay parameters of the filterbanks. Hence, higher stopband attenuation can still be achieved at low system delay. The design of the proposed low-delay filterbanks is formulated as a complex polynomial approximation problem, which can be solved by the Remez exchange algorithm or analytic formula with very low complexity. In addition, the orders and delay parameters can be estimated from the given filter specifications using a simple empirical formula. Therefore, low-delay two-channel PR filterbanks with flexible stopband attenuation and cutoff frequencies can be designed using existing filter design algorithms. The generalization of the present approach to the design of a class of wavelet bases associated with these low-delay filterbanks and its multiplier-less implementation using the sum of powers-of-two coefficients are also studied.published_or_final_versio