1,906 research outputs found

    Analog Circuits in Ultra-Deep-Submicron CMOS

    Get PDF
    Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

    Analog/RF Circuit Design Techniques for Nanometerscale IC Technologies

    Get PDF
    CMOS evolution introduces several problems in analog design. Gate-leakage mismatch exceeds conventional matching tolerances requiring active cancellation techniques or alternative architectures. One strategy to deal with the use of lower supply voltages is to operate critical parts at higher supply voltages, by exploiting combinations of thin- and thick-oxide transistors. Alternatively, low voltage circuit techniques are successfully developed. In order to benefit from nanometer scale CMOS technology, more functionality is shifted to the digital domain, including parts of the RF circuits. At the same time, analog control for digital and digital control for analog emerges to deal with current and upcoming imperfections

    A review of advances in pixel detectors for experiments with high rate and radiation

    Full text link
    The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

    Designing analog circuits in CMOS

    Get PDF
    The evolution in CMOS technology dictated by Moore's Law is clearly beneficial for designers of digital circuits, but it presents difficult challenges, such as lowered nominal supply voltages, for their peers in the analog world who want to keep pace with this rapid progression. This article discusses a number of significant items for analog designs in modern and future CMOS processes and possible ways to maintain performance

    A large dynamic range radiation-tolerant analog memory in a quarter- micron CMOS technology

    Get PDF
    An analog memory prototype containing 8*128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage V/sub DD/ is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is +or-0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 100 kGy (SiO/sub 2/), and they do not degrade after irradiation. (15 refs)

    Radiation Effects in CMOS Isolation Oxides: Differences and Similarities With Thermal Oxides

    Get PDF
    Radiation effects in thick isolation oxides of modern CMOS technologies are investigated using dedicated test structures designed using two commercial foundries. Shallow Trench Isolation and Pre-Metal Dielectric are studied using electrical measurements performed after X-ray irradiations and isochronal annealing cycles. This paper shows that trapping properties of such isolation oxides can strongly differ from those of traditional thermal oxides usually used to process the gate oxide of Metal Oxide Semiconductor Field Effect Transistors. Buildup and annealing of both radiation-induced oxide-trap charge and radiation-induced interface traps are discussed as a function of the oxide type, foundry and bias condition during irradiation. Radiation-induced interface traps in such isolation oxides are shown to anneal below 100°C contrary to what is usually observed in thermal oxides. Implications for design hardening and radiation tests of CMOS Integrated Circuits are discussed

    Single Event Effects in the Pixel readout chip for BTeV

    Get PDF
    In future experiments the readout electronics for pixel detectors is required to be resistant to a very high radiation level. In this paper we report on irradiation tests performed on several preFPIX2 prototype pixel readout chips for the BTeV experiment exposed to a 200 MeV proton beam. The prototype chips have been implemented in commercial 0.25 um CMOS processes following radiation tolerant design rules. The results show that this ASIC design tolerates a large total radiation dose, and that radiation induced Single Event Effects occur at a manageable level.Comment: 15 pages, 6 Postscript figure
    • …
    corecore