A Novel Three-Point Modulation Technique for Fractional-N Frequency Synthesizer Applications

This paper presents a novel three-point modulation technique for fractional-N frequency synthesizer applications. Convention modulated fractional-N frequency synthesizers suffer from quantization noise, which degrades not only the phase noise performance but also the modulation quality. To solve this problem, this work proposes a three-point modulation technique, which not only cancels the quantization noise, but also markedly boosts the channel switching speed. Measurements reveal that the implemented 2.4 GHz fractional-N frequency synthesizer using three-point modulation can achieve a 2.5 Mbps GFSK data rate with an FSK error rate of only 1.4 %. The phase noise is approximately -98 dBc/Hz at a frequency offset of 100 kHz. The channel switching time is only 1.1 μs with a frequency step of 80 MHz. Comparing with conventional two-point modulation, the proposed three-point modulation greatly improves the FSK error rate, phase noise and channel switching time by about 10 %, 30 dB and 126 μs, respectively

Sub-100 attoseconds optics-to-microwave synchronization

We use two fiber-based femtosecond frequency combs and a low-noise carrier suppression phase detection system to characterize the optical to microwave synchronization achievable with such frequency divider systems. By applying specific noise reduction strategies, a residual phase noise as low as -120 dBc/Hz at 1 Hz offset frequency from a 11.55 GHz carrier is measured. The fractional frequency instability from a single optical-to-frequency divider is 1.1E-16 at 1 s averaging down to below 2E-19 after only 1000 s. The corresponding rms time deviation is lower than 100 attoseconds up to 1000 s averaging duration.Comment: 4 pages, 3 figure

Generation of Ultrastable Microwaves via Optical Frequency Division

There has been increased interest in the use and manipulation of optical fields to address challenging problems that have traditionally been approached with microwave electronics. Some examples that benefit from the low transmission loss, agile modulation and large bandwidths accessible with coherent optical systems include signal distribution, arbitrary waveform generation, and novel imaging. We extend these advantages to demonstrate a microwave generator based on a high-Q optical resonator and a frequency comb functioning as an optical-to-microwave divider. This provides a 10 GHz electrical signal with fractional frequency instability <8e-16 at 1 s, a value comparable to that produced by the best microwave oscillators, but without the need for cryogenic temperatures. Such a low-noise source can benefit radar systems, improve the bandwidth and resolution of communications and digital sampling systems, and be valuable for large baseline interferometry, precision spectroscopy and the realization of atomic time

Integrated radio frequency synthetizers for wireless applications

This thesis consists of six publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis concentrates on the design of phase-locked loop radio frequency synthesizers for wireless applications. In particular, the focus is on the implementation of the prescaler, the phase detector, and the chargepump. This work reviews the requirements set for the frequency synthesizer by the wireless standards, and how these requirements are derived from the system specifications. These requirements apply to both integer-N and fractional-N synthesizers. The work also introduces the special considerations related to the design of fractional-N phase-locked loops. Finally, implementation alternatives for the different building blocks of the synthesizer are reviewed. The presented work introduces new topologies for the phase detector and the chargepump, and improved topologies for high speed CMOS prescalers. The experimental results show that the presented topologies can be successfully used in both integer-N and fractional-N synthesizers with state-of-the-art performance. The last part of this work discusses the additional considerations that surface when the synthesizer is integrated into a larger system chip. It is shown experimentally that the synthesizer can be successfully integrated into a complex transceiver IC without sacrificing the performance of the synthesizer or the transceiver.reviewe

An Analog Phase Interpolation Based Fractional-N PLL

A novel phase-locked loop topology is presented. Compared to conventional designs, this architecture aims to increase frequency resolution and reduce quantization noise while maintaining the fractional-N benefits of high bandwidth and low phase noise up-conversion. This is achieved utilizing a feedforward mechanism for offset cancellation from the integer-N frequency. The design is implemented in a 0.13μm CMOS process technology. A frequency resolution of 1.16Hz is achieved on a 5GHz differential delay cell VCO with a 100MHz reference oscillator. A ping-pong swallow counter topology alleviates pipeline latency to achieve 1-64 divide ratios. A digital pulse generator and nested phase-frequency detector provide tunable offset cancellation. A 5-bit current-steering DAC capable of 200ps pulses reduces output spurs. Theoretical calculations and Simulink modeling provides insight to the effects of non idealities in the system. Test structures and loop configurability are programmed via SPI interface through a custom GUI and prototype PCB

ULTRA-LOW-JITTER, MMW-BAND FREQUENCY SYNTHESIZERS BASED ON A CASCADED ARCHITECTURE

Department of Electrical EngineeringThis thesis presents an ultra-low-jitter, mmW-band frequency synthesizers based on a cascaded architecture. First, the mmW-band frequency synthesizer based on a CP PLL is presented. At the first stage, the CP PLL operating at GHz-band frequencies generated low-jitter output signals due to a high-Q VCO. At the second stage, an ILFM operating at mmW-band frequencies has a wide injection bandwidth, so that the jitter performance of the mmW-band output signals is determined by the GHz-range PLL. The proposed ultra-low-jitter, mmW-band frequency synthesizer based on a CP PLL, fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 206 fs and an IPN of ???31 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively. However, due to a large in-band phase noise contribution of a PFD and a CP in the CP PLL, this first stage was difficult to achieve an ultra-low in-band phase noise. Second, to improve the in-band phase noise further, the mmW-band frequency synthesizer based on a digital SSPLL is presented. At the first stage, the digital SSPLL operating at GHz-band frequencies generated ultra-low-jitter output signals due to its sub-sampling operation and a high-Q GHz VCO. To minimize the quantization noise of the voltage quantizer in the digital SSPLL, this thesis presents an OSVC as a voltage quantizer while a small amount of power was consumed. The proposed ultra-low-jitter, mmW-band frequency synthesizer fabricated in a 65-nm CMOS technology, generated output signals from GHz-band frequencies to mmW-band frequencies, achieving an RMS jitter of 77 fs and an IPN of ???40 dBc. The active silicon area and the total power consumption were 0.32 mm2 and 42 mW, respectively.clos