Low-power synthesis flow for regular processor design

Flow around an ICE2 high-speed train exiting a tunnel under the influence of a wind gust has been studied using numerical technique called detached eddy simulation. A wind gust boundary condition was derived to approximate previous experimental observations. The body of the train includes most important details including bogies, plugs, inter-car gaps and rotating wheels on the rail. The maximal yawing and rolling moments which possibly can cause a derailment or overturning were found to occur when approximately one third and one half of the train, respectively, has left the tunnel. These are explained by development of a strong vortex trailing along the upper leeward edge of the train. All aerodynamic forces and moments were monitored during the simulation and the underlying flow structures and mechanisms are explained

Design and FPGA Implementation of CORDIC-based 8-point 1D DCT Processor

CORDIC or CO-ordinate Rotation DIgital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. Using a prescribed sequence of conditional additions or subtractions the CORDIC arithmetic unit can be controlled to solve either of the following equations: Y’=K (Ycos λ+ Xsin λ) X’=K (Xcos λ - Ysin λ); where K is a constant In this project: • A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 10.1. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by ChipScopePro analysis of the output logic waveforms was performed. • Using this CORDIC core a DCT processor was designed to calculate the 8-point 1D DCT. The functionality and operational correctness of this processor was tested, first on the test-bench and then via ChipScopePro analysis, post FPGA implementation. The output obtained in both the cases was compared with the actual values to test for consistency and the percentage of accuracy was established. Power consumption and FPGA resource utilization were observed. The results obtained were discussed