Maze Mouse

This report is intended to provide an insight view of the Maze Mouse project. The first chapter serves astheintroduction to theproject, which covers the background of study, problem statement, and objectives and scope of study. The objective of this project is to produce a prototype of a mouse that can find itsown way out of a maze smoothly, butnot necessarily very quickly. This will be explained later in the report. This project requires strong basics in electronics, covering three important aspects of the mouse which are microcontroller, infrared sensor and stepper motor. The earlier partof the second chapter describes the details of the Sterling Mouse, an example of a mazemouse. The Sterling Mouse was created by Nick Smith as a participant in the Micromouse Competition held in the United States. The third chapter of this report presents the methodology used in completing thisMaze Mouse project. This includes the purchasing and procurement of the components, circuit construction, programming and integration of the mouse's separate circuits. In the next chapter, you will be provided with the details of the project work, which focuses on howthe prototype gets to work

Maze Mouse

This report is intended to provide an insight view of the Maze Mouse project. The first chapter serves astheintroduction to theproject, which covers the background of study, problem statement, and objectives and scope of study. The objective of this project is to produce a prototype of a mouse that can find itsown way out of a maze smoothly, butnot necessarily very quickly. This will be explained later in the report. This project requires strong basics in electronics, covering three important aspects of the mouse which are microcontroller, infrared sensor and stepper motor. The earlier partof the second chapter describes the details of the Sterling Mouse, an example of a mazemouse. The Sterling Mouse was created by Nick Smith as a participant in the Micromouse Competition held in the United States. The third chapter of this report presents the methodology used in completing thisMaze Mouse project. This includes the purchasing and procurement of the components, circuit construction, programming and integration of the mouse's separate circuits. In the next chapter, you will be provided with the details of the project work, which focuses on howthe prototype gets to work

Measurement and Analysis of Power in Hybrid System

Application with renewable energy  sources  such   as solar cell array, wind turbines, or fuel cells have increased significantly during the past decade. To obtain the clean energy, we are using the hybrid solar-wind power generation. Consumers prefer quality power from suppliers. The quality of power can be measured by using parameters such as voltage sag, harmonic and power factor.   To   obtain   quality   power   we   have different topologies. In our paper we present a new possible topology which improves power quality. This paper presents modeling analysis and design of a pulse width modulation voltage source inverter (PWM-VSI) to be connected between sources, which supplies energy from a hybrid solar wind energy system to the ac grid. The objective of this paper is to show that, with an adequate control, the converter not only can transfer the dc from hybrid solar wind energy system, but also can improve the power factor and quality power of electrical system. Whenever a disturbance occurs on load side, this disturbance can be minimized using open loop and closed loop control systems

Design of asynchronous microprocessor for power proportionality

PhD ThesisMicroprocessors continue to get exponentially cheaper for end users following Moore’s law, while the costs involved in their design keep growing, also at an exponential rate. The reason is the ever increasing complexity of processors, which modern EDA tools struggle to keep up with. This makes further scaling for performance subject to a high risk in the reliability of the system. To keep this risk low, yet improve the performance, CPU designers try to optimise various parts of the processor. Instruction Set Architecture (ISA) is a significant part of the whole processor design flow, whose optimal design for a particular combination of available hardware resources and software requirements is crucial for building processors with high performance and efficient energy utilisation. This is a challenging task involving a lot of heuristics and high-level design decisions. Another issue impacting CPU reliability is continuous scaling for power consumption. For the last decades CPU designers have been mainly focused on improving performance, but “keeping energy and power consumption in mind”. The consequence of this was a development of energy-efficient systems, where energy was considered as a resource whose consumption should be optimised. As CMOS technology was progressing, with feature size decreasing and power delivered to circuit components becoming less stable, the energy resource turned from an optimisation criterion into a constraint, sometimes a critical one. At this point power proportionality becomes one of the most important aspects in system design. Developing methods and techniques which will address the problem of designing a power-proportional microprocessor, capable to adapt to varying operating conditions (such as low or even unstable voltage levels) and application requirements in the runtime, is one of today’s grand challenges. In this thesis this challenge is addressed by proposing a new design flow for the development of an ISA for microprocessors, which can be altered to suit a particular hardware platform or a specific operating mode. This flow uses an expressive and powerful formalism for the specification of processor instruction sets called the Conditional Partial Order Graph (CPOG). The CPOG model captures large sets of behavioural scenarios for a microarchitectural level in a computationally efficient form amenable to formal transformations for synthesis, verification and automated derivation of asynchronous hardware for the CPU microcontrol. The feasibility of the methodology, novel design flow and a number of optimisation techniques was proven in a full size asynchronous Intel 8051 microprocessor and its demonstrator silicon. The chip showed the ability to work in a wide range of operating voltage and environmental conditions. Depending on application requirements and power budget our ASIC supports several operating modes: one optimised for energy consumption and the other one for performance. This was achieved by extending a traditional datapath structure with an auxiliary control layer for adaptable and fault tolerant operation. These and other optimisations resulted in a reconfigurable and adaptable implementation, which was proven by measurements, analysis and evaluation of the chip.EPSR

Design and Development of Microcontroller System, Embedded Circuits and Applications

Not availabl

DETECTION AND REMOVAL OF DUST PARTICLES IN PIPELINES USING 3-D MEMS

Currently, the detection of dust particles is realized through manual sampling. Thus it is desirable to develop an automated online technique. Generally, industries run with the help of pipelines through which liquid can flow. The main aim of the work is to detect the dust particles which are present inside the pipeline when liquid is flowing through it. Distributed Acoustic Sensing (DAS) is a recent addition to the pipeline security world. Opta sense system is designed to prevent the damage in pipeline by providing the advance warning to the concern department and make them alert. The dust particles are detected by using MEMS, which can sense in three axis (Heat, Vibration, Movement). It is identified by the IR sensor. The approach can also be simulated by using MATLAB

Characteristics and development report for the SA3871 Intent Controller application specific integrated circuit (ASIC)

This report describes the design and development activities that were involved in the SA3871 Intent Controller ASIC. The SA3871 is a digital gate array component developed for the MC4396 Trajectory Sensing Signal Generator for use in the B61-3/4/10 system as well as a possible future B61-MAST system

Circuit DDS en format XBee

El present document recull, per una banda, la memòria tècnica i constructiva d'un circuit oscil·lador basat en DDS i gestionat per un microcontrolador, el qual permet la programació d'aquest oscil·lador de manera versàtil, utilitzant un seguit d'instruccions properes al usuari programador. El circuit és compatible amb el footprint dels mòduls XBee. Per altra banda també consta de la documentació d'usuari i els exemples adequats per al seu ús. El dispositiu té la finalitat de contribuir a l'enginyeria de sistemes electrònics, aportant una peça habitual en múltiples aplicacions i dotar-la de la flexibilitat suficient per tal d'adaptar-se al major ventall d'aplicacions possible