Autonomic Management of Reconfigurable Embedded Systems using Discrete Control: Application to FPGA

This paper targets the autonomic management of dynamically partially reconfigurable hardware architectures based on FPGAs. Such hardware-level autonomic computing has been less often studied than at software-level. We consider control techniques to model the considered behaviours of the computing system and derive a controller for the control objective enforcement. Discrete Control modelled with Labelled Transition Systems is employed in this paper. Such models are amenable to Discrete Controller Synthesis algorithms that can automatically generate a controller enforcing the correct behaviours of a controlled system. A general modelling framework is proposed for the control of FPGA based computing systems. We consider system application described as task graphs and FPGA as a set of reconfigurable areas that can be dynamically partially reconfigured to execute tasks. We encode the computation of an autonomic manager as a DCS problem w.r.t. multiple constraints and objectives e.g., mutual exclusion of resource uses, power cost minimization. We validate our models and manager computations by using the BZR language and an experimental demonstrator implemented on a Xilinx FPGA platform.Nous traitons de la gestion autonomique des architectures matérielles dynamique- ment et partiellement reconfigurables á base de FPGAs. Cette forme d'informatique autonomique au niveau matériel a été moins souvent étudié qu'au niveau logiciel. Nous considérons des tech- niques de contrôle pour modéliser les comportements du système de calcul et pour dériver un contrôleur pour le maintien de l'objectif de contrôle. Nous utilisons des techniques de contrôle discret modélisé avec des systèmes de transition étiquetés. Ces modèles se prêtent à une algorith- mique de synthèse de contrôleurs discrets (SCD) qui peut générer automatiquement un contrôleur qui force les comportements corrects d'un système contrôlé. Un cadre général de modélisation est proposé pour le contrôle des systèmes informatiques à base de FPGA. Nous considérons que l'application est décrite par un graphes de tâches, et le FPGA comme un ensemble de zones reconfigurables, qui peuvent être dynamiquement et partiellement reconfigurées pour exécuter des tâches. Nous formulons le calcul d'un gestionnaire autonomique comme un problème de SCD concernant des contraintes et objectifs multiples, par exemple, l'exclusion mutuelle de l'utilisation des ressources, la minimisation du coût en énergie. Nous validons nos modèles et les calculs du gestionnaire en utilisant le langage BZR et un démonstrateur expérimental mis en œuvre sur une plate-forme FPGA Xilinx

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

New Design Techniques for Dynamic Reconfigurable Architectures

L'abstract è presente nell'allegato / the abstract is in the attachmen

Octopus - an energy-efficient architecture for wireless multimedia systems

Multimedia computing and mobile computing are two trends that will lead to a new application domain in the near future. However, the technological challenges to establishing this paradigm of computing are non-trivial. Personal mobile computing offers a vision of the future with a much richer and more exciting set of architecture research challenges than extrapolations of the current desktop architectures. In particular, these devices will have limited battery resources, will handle diverse data types, and will operate in environments that are insecure, dynamic and which vary significantly in time and location. The approach we made to achieve such a system is to use autonomous, adaptable modules, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules that is placed in the data streams. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies