Design Techniques for High Speed Low Voltage and Low Power Non-Calibrated Pipeline Analog to Digital Converters

The profound digitization of modern microelectronic modules made Analog-to- Digital converters (ADC) key components in many systems. With resolutions up to 14bits and sampling rates in the 100s of MHz, the pipeline ADC is a prime candidate for a wide range of applications such as instrumentation, communications and consumer electronics. However, while past work focused on enhancing the performance of the pipeline ADC from an architectural standpoint, little has been done to individually address its fundamental building blocks. This work aims to achieve the latter by proposing design techniques to improve the performance of these blocks with minimal power consumption in low voltage environments, such that collectively high performance is achieved in the pipeline ADC. Towards this goal, a Recycling Folded Cascode (RFC) amplifier is proposed as an enhancement to the general performance of the conventional folded cascode. Tested in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18?m Complementary Metal Oxide Semiconductor (CMOS) technology, the RFC provides twice the bandwidth, 8-10dB additional gain, more than twice the slew rate and improved noise performance over the conventional folded cascode-all at no additional power or silicon area. The direct auto-zeroing offset cancellation scheme is optimized for low voltage environments using a dual level common mode feedback (CMFB) circuit, and amplifier differential offsets up to 50mV are effectively cancelled. Together with the RFC, the dual level CMFB was used to implement a sample and hold amplifier driving a singleended load of 1.4pF and using only 2.6mA; at 200MS/s better than 9bit linearity is achieved. Finally a power conscious technique is proposed to reduce the kickback noise of dynamic comparators without resorting to the use of pre-amplifiers. When all techniques are collectively used to implement a 1Vpp 10bit 160MS/s pipeline ADC in Semiconductor Manufacturing International Corporation (SMIC) 0.18[mu]m CMOS, 9.2 effective number of bits (ENOB) is achieved with a near Nyquist-rate full scale signal. The ADC uses an area of 1.1mm2 and consumes 42mW in its analog core. Compared to recent state-of-the-art implementations in the 100-200MS/s range, the presented pipeline ADC uses the least power per conversion rated at 0.45pJ/conversion-step

8-Phase Ring oscillator for modern receivers

The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers

Design and Optimization of Low-power Level-crossing ADCs

This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit