Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply

Circuits and Systems for On-Chip RF Chemical Sensors and RF FDD Duplexers

Integrating RF bio-chemical sensors and RF duplexers helps to reduce cost and area in the current applications. Furthermore, new applications can exist based on the large scale integration of these crucial blocks. This dissertation addresses the integration of RF bio-chemical sensors and RF duplexers by proposing these initiatives. A low power integrated LC-oscillator-based broadband dielectric spectroscopy (BDS) system is presented. The real relative permittivity ε’r is measured as a shift in the oscillator frequency using an on-chip frequency-to-digital converter (FDC). The imaginary relative permittivity ε”r increases the losses of the oscillator tank which mandates a higher dc biasing current to preserve the same oscillation amplitude. An amplitude-locked loop (ALL) is used to fix the amplitude and linearize the relation between the oscillator bias current and ε”r. The proposed BDS system employs a sensing oscillator and a reference oscillator where correlated double sampling (CDS) is used to mitigate the impact of flicker noise, temperature variations and frequency drifts. A prototype is implemented in 0.18 µm CMOS process with total chip area of 6.24 mm^2 to operate in 1-6 GHz range using three dual bands LC oscillators. The achieved standard deviation in the air is 2.1 ppm for frequency reading and 110 ppm for current reading. A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky SAW and BAW duplexers in 3G/4G cellular transceivers. A balancing network creates a replica of the transmitter signal for cancellation at the input of a single-ended low noise amplifier (LNA) to isolate the receive path from the transmitter. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra balun at the antenna side. The duplexer achieves around 50 dB TX-RX isolation within 1.6-2.2 GHz range up to 22 dBm. The cascaded noise figure of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in 0.18 µm CMOS process and occupy an active area of 0.35 mm^2

Design and investigation of nanometric integrated circuits for all-digital frequency synthesisers

Disertacijoje nagrinėjami daugiajuosčių dažnio sintezatorių blokai, modeliai bei jų kūrimas taikant nanometrines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad taikant nanometrines technologijas visiškai skaitmeniniai dažnio sintezatoriai įgalina gauti parametrus, reikiamus daugiajuosčiams belai- džio ryšio siųstuvams-imtuvams. Darbo tikslas – sukurti visiškai skaitmeninio dažnio sintezatoriaus blokus, kuriuos naudojant galima pasiekti reikiamus sinte- zatoriaus, skirto daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams, paramet- rus taikant nanometrines integrinių grandynų gamybos technologijas. Darbe išsp- ręsti tokie uždaviniai: ištirtos dažnio sintezatorių struktūros ir sukurta struktūra, tinkama įgyvendinti taikant nanometrines technologijas, sukurti ir ištirti siūlomos struktūros sintezatorių sudarančių blokų modeliai ir integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatū- ros ir autoriaus publikacijų disertacijos tema sąrašai ir keturi priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašo- mas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma ty- rimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, gi- namieji teiginiai bei disertacijos struktūra. Pirmajame skyriuje apžvelgiamos dažnio sintezatorių rūšys, aprašomi pag- rindiniai dažnio sintezatorių parametrai ir dažniausiai naudojamos kokybės funk- cijos. Apžvelgiami dažnio sintezatorių modeliai ir jų veikimas fazės ir dažnio sri- tyse. Aprašomi visiškai skaitmeninio dažnio sintezatoriaus triukšmų šaltiniai. Skyriaus pabaigoje suformuluojami disertacijos uždaviniai. Antrajame skyriuje pasiūlyta ir taikoma nauja kokybės funkcija, leidžianti at- likti daugiajuosčių dažnio sintezatorių palyginamąją analizę. Iškeliami reikalavi- mai pagrindiniams sintezatoriaus blokams, nagrinėjami laikinio skaitmeninio kei- tiklio skiriamosios gebos didinimo būdai, sukurtas naujas laikinio skaitmeninio keitiklio modelis. Siūloma dažnio sintezatoriaus struktūra daugiajuosčiams siųs- tuvams-imtuvams. Trečiajame skyriuje pagal iškeltus reikalavimus daugiajuosčio dažnio sinte- zatoriaus blokams, taikant kompiuterinių skaičiavimų ir eksperimentinius meto- dus yra kuriami ir tiriami laikinio skaitmeninio keitiklio, skaitmeniniu būdu val- domo generatoriaus bei skaitmeninio filtro integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 4 – mokslo žurna- luose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 1 – tarp- tautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analytics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duo- menų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti devyniose mokslinėse konferencijose Lietuvoje ir užsienyje

Design and investigation of nanometric and submicron integrated circuits for voltage and digital controlled oscillators

Disertacijoje nagrinėjama LC-ĮVG ir LC-SVG, architektūros, modeliai bei jų kūrimas taikant nanometrines ir submikronines integrinių grandynų technologijas. Iškeliama ir įrodoma hipotezė, kad tinkamos architektūros parinkimas ir integrinių grandynų technologijų taikymas įgalina sukurti reikiamų parametrų ir kokybės 2–10 GHz įtampa ir skaitmeniniu būdu valdomus generatorius nanometriniuose ir submikroniniuose integriniuose grandynuose. Darbo tikslas – sukurti 2–10 GHz LC-ĮVG ir LC-SVG blokus nanometrinėse bei submikroninėse KMOP integrinių grandynų technologijose, leidžiančius pasiekti reikiamus parametrus skirtus daugiastandarčiams daugiajuosčiams belaidžio ryšio siųstuvams-imtuvams iki 10 GHz. Darbe išspręsti tokie uždaviniai: ištirtos LC-ĮVG ir LC-SVG architektūros skirtingose integrinių grandynų KMOP technologijose ir parinkta optimali architektūra integrinių grandynų sukūrimui, pasiūlytos naujos kokybės funkcijos skirtos LC-ĮVG ir LC-SVG palyginamajai analizei, sukurti ir ištirti LC-ĮVG ir LC-SVG integriniai grandynai. Disertaciją sudaro įvadas, trys skyriai, bendrosios išvados, naudotos literatūros ir autoriaus publikacijų disertacijos tema sąrašai ir trys priedai. Įvadiniame skyriuje aptariama tiriamoji problema, darbo aktualumas, aprašomas tyrimų objektas, formuluojamas darbo tikslas bei uždaviniai, aprašoma tyrimų metodika, darbo mokslinis naujumas, darbo rezultatų praktinė reikšmė, ginamieji teiginiai. Įvado pabaigoje pristatomos disertacijos tema autoriaus paskelbtos publikacijos ir pranešimai konferencijose bei disertacijos struktūra. Pirmajame skyriuje analizuojamos dažnio generatorių architektūros, jų pritaikymas bei jų pagrindiniai parametrai. Pateikiami pagrindiniai dažnio generatorių parametrai. Apžvelgiamos kokybės funkcijos, nusakančios dažnio generatorių pagrindinius parametrus skirtus palyginamajai analizei. Antrajame skyriuje pateikiamos naujos FOMTT FOMT2 kokybės funkcijos, kuriomis remiantis vertinami valdomo dažnio generatorių pagrindiniai parametrai palyginamajai analizei. Taip pat pateikiami induktyvumo ritės kokybės gerinimo būdai. Trečiajame skyriuje, taikant kompiuterinių skaičiavimų ir eksperimentinius metodus yra kuriami ir tiriami įtampa ir skaitmeniniu būdu valdomų generatorių bei papildomų blokų integriniai grandynai. Disertacijos tema yra atspausdinti 7 moksliniai straipsniai: 2 – mokslo žurnaluose, įtrauktuose į Clarivate Analytics Web of Science duomenų bazę, 3 – tarptautinių konferencijų medžiagoje, įtrauktoje į Clarivate Analy-tics Proceedings duomenų bazę, 2 – mokslo žurnaluose, referuojamuose kitose tarptautinėse duomenų bazėse. Disertacijoje atliktų tyrimų rezultatai buvo paskelbti dvylikoje mokslinių konferencijų Lietuvoje ir užsienyje.Disertacij

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO

Ultra-Low Power Transmitter and Power Management for Internet-of-Things Devices

Two of the most critical components in an Internet-of-Things (IoT) sensing and transmitting node are the power management unit (PMU) and the wireless transmitter (Tx). The desire for longer intervals between battery replacements or a completely self-contained, battery-less operation via energy harvesting transducers and circuits in IoT nodes demands highly efficient integrated circuits. This dissertation addresses the challenge of designing and implementing power management and Tx circuits with ultra-low power consumption to enable such efficient operation. The first part of the dissertation focuses on the study and design of power management circuits for IoT nodes. This opening portion elaborates on two different areas of the power management field: Firstly, a low-complexity, SPICE-based model for general low dropout (LDO) regulators is demonstrated. The model aims to reduce the stress and computation times in the final stages of simulation and verification of Systems-on-Chip (SoC), including IoT nodes, that employ large numbers of LDOs. Secondly, the implementation of an efficient PMU for an energy harvesting system based on a thermoelectric generator transducer is discussed. The PMU includes a first-in-its-class LDO with programmable supply noise rejection for localized improvement in the suppression. The second part of the dissertation addresses the challenge of designing an ultra- low power wireless FSK Tx in the 900 MHz ISM band. To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner PA, the Tx showed a measured energy efficiency of 0.2 nJ/bit and a normalized energy efficiency of 3.1 nJ/(bit∙mW) when operating at output power levels up to -10 dBm and data rates of 3 Mbps. To close this dissertation, the implementation of a supply-noise tolerant BiCMOS ring-oscillator is discussed. The combination of a passive, high-pass feedforward path from the supply to critical nodes in the selected delay cell and a low cost LDO allow the oscillator to exhibit power supply noise rejection levels better than –33 dB in experimental results

Low-Power High Data-Rate Wireless Transmitter For Medical Implantable Devices

RÉSUMÉ Les émetteurs-récepteurs radiofréquences (RF) sont les circuits de communication les plus communs pour établir des interfaces home-machine dédiées aux dispositifs médicaux implantables. Par exemple, la surveillance continue de paramètres de santé des patients souffrant d'épilepsie nécessite un étage de communication sans-fil capable de garantir un transfert de données rapide, en temps réel, à faible puissance tout en étant implémenté dans un faible volume. La consommation de puissance des dispositifs implantables implique une durée de vie limitée de la batterie qui nécessite alors une chirurgie pour son remplacement, a moins qu’une technique de transfert de puissance sans-fil soit utilisée pour recharger la batterie ou alimenter l’implant a travers les tissus humains. Dans ce projet, nous avons conçu, implémenté et testé un émetteur RF à faible puissance et haut-débit de données opérant à 902-928 MHz de la bande fréquentielle industrielle-scientifique-médicale (ISM) d’Amérique du Nord. Cet émetteur fait partie d'un système de communication bidirectionnel dédié à l’interface sans-fil des dispositifs électroniques implantables et mettables et bénéficie d’une nouvelle approche de modulation par déplacement de fréquence (FSK). Les différentes étapes de conception et d’implémentation de l'architecture proposée pour l'émetteur sont discutées et analysées dans cette thèse. Les blocs de circuits sont réalisés suivant les équations dérivées de la modulation FSK proposée et qui mènera à l'amélioration du débit de données et de la consommation d'énergie. Chaque bloc est implémenté de manière à ce que la consommation d'énergie et la surface de silicium nécessaires soient réduites. L’étage de modulation et le circuit mélangeur ne nécessitent aucun courant continu grâce à leur structure passive.Parmi les circuits originaux, un oscillateur en quadrature contrôlé-en-tension (QVCO) de faible puissance est réalisé pour générer des signaux différentiels en quadrature, rail-à-rail avec deux gammes de fréquences principales de 0.3 à 11.5 MHz et de 3 à 40 MHz. L'étage de sortie énergivore est également amélioré et optimisé pour atteindre une efficacité de puissance de ~ 37%. L'émetteur proposé a été implémenté et fabriqué à la suite de simulations post-layout approfondies.----------ABSTRACT Wireless radio frequency (RF) transceivers are the most common communication front-ends used to realize the human-machine interfaces of medical devices. Continuous monitoring of body behaviour of patients suffering from Epilepsy, for example, requires a wireless communication front-end capable of maintaining a fast, real-time and low-power data communication while implemented in small size. Power budget limitation of the implantable and wearable medical devices obliges engineers to replace or recharge the battery cell through frequent medial surgeries or other power transfer techniques. In this project, a low-power and high data-rate RF transmitter (Tx) operating at North-American Industrial-Scientific-Medical (ISM) frequency band (902-928 MHz) is designed, implemented and tested. This transmitter is a part of a bi-directional transceiver dedicated to the wireless interface of implantable and wearable medical devices and benefits from a new efficient Frequency-Shift Keying (FSK) modulation scheme. Different design and implementation stages of the proposed transmitter architecture are discussed and analyzed in this thesis. The building blocks are realized according to the equations derived from the proposed FSK modulation, which results in improvement in data-rate and power consumption. Each block is implemented such that the power consumption and needed chip area are lowered while the modulation block and the mixer circuit require no DC current due to their passive structure. Among the original blocks, a low-power quadrature voltage-controlled oscillator (QVCO) is achieved to provide differential quadrature rail-to-rail signals with two main frequency ranges of 0.3-11.5 MHz and 3-40 MHz. The power-hungry output stage is also improved and optimized to achieve power efficiency of ~37%. The proposed transmitter was implemented and fabricated following deep characterisation by post-layout simulation. Both simulation and measurement results are discussed and compared with state-of-the-art transmitters showing the contribution of this work in this very popular research field. The Figure-Of-Merit (FOM) was improved, meaning mainly increasing the data-rate and lowering the power consumption of the circuit. The transmitter is implemented using 130 nm CMOS technology with 1.2 V supply voltage. A data-rate of 8 Mb/s was measured while consuming 1.4 mA and resulting in energy consumption of 0.21 nJ/b. The fabricated transmitter has small active silicon area of less than 0.25 mm2

A high efficiency BPSK receiver for short range wireless network

In this paper, a 910MHz high efficiency BPSK receiver is presented with Colpitts oscillator for short range wireless network. In this research, with injection-lock technique and using Colpitts oscillator, the efficiency of receiver has been improved. And also, behavior of an oscillator under injection of another signal has been investigated. Also, variation of output signal amplitude versus injected signal phase variation, the effect of varying the amplitude of injected signal and quality factor of the oscillator has been investigated. The designed receiver has 0.474 mW dc power and -60 dBm sensitivity. Data rate of receiver is 5 Mbps. The FOM of receiver is 94 pJ/bit. This receiver was designed and simulated in 0.18 μm RFCMOS technology. This proposed receiver can be used in short range wireless network for example, Wireless Body array network and wireless sensor network

RF CMOS Oscillators for Modern Wireless Applications

While mobile phones enjoy the largest production volume ever of any consumer electronics products, the demands they place on radio-frequency (RF) transceivers are particularly aggressive, especially on integration with digital processors, low area, low power consumption, while being robust against process-voltage-temperature variations. Since mobile terminals inherently operate on batteries, their power budget is severely constrained. To keep up with the ever increasing data-rate, an ever-decreasing power per bit is required to maintain the battery lifetime. The RF oscillator is the second most power-hungry block of a wireless radio (after power amplifiers). Consequently, any power reduction in an RF oscillator will greatly benefit the overall power efficiency of the cellular transceiver. Moreover, the RF oscillators' purity limits the transceiver performance. The oscillator's phase noise results in power leakage into adjacent channels in a transmit mode and reciprocal mixing in a receive mode. On the other hand, the multi-standard and multi-band transceivers that are now trending demand wide tuning range oscillators. However, broadening the oscillator’s tuning range is usually at the expense of die area (cost) or phase noise. The main goal of this book is to bring forth the exciting and innovative RF oscillator structures that demonstrate better phase noise performance, lower cost, and higher power efficiency than currently achievable. Technical topics discussed in RF CMOS Oscillators for Modern Wireless Applications include: Design and analysis of low phase-noise class-F oscillators Analyze a technique to reduce 1/f noise up-conversion in the oscillators Design and analysis of low power/low voltage oscillators Wide tuning range oscillators Reliability study of RF oscillators in nanoscale CMO