289 research outputs found
金属/絶縁体/半導体(MIS)構造を用いたn型GaNの接触抵抗に関する研究
Tohoku University博士(工学)thesi
Effects of Thermal Boundary Resistance on Thermal Management of Gallium-Nitride-Based Semiconductor Devices: A Review
Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices
Zuverlässigkeit von AlGaN/GaN-Leistungsbauelementen
Zur Ermittlung der Zuverlässigkeit von leistungselektronischen Bauelementen sind eine Reihe von Testverfahren etabliert. In Lastwechseltests ist die Temperatur der dominierende Parameter für bekannte Lebensdauermodelle. Aufgrund des Aufbaus und der Eigenschaften von AlGaN/GaN-Bauelementen ist es notwendig, neue Methoden zur Temperaturbestimmung zu etablieren. Die Untersuchungen berücksichtigen dabei verschiedene Bauteilkonzepte.
Dazu gehören High Electron Mobility Transistors (HEMT) mit Schottky/p-Gate, für
die eine Verwendung des Gateleckstromes als temperatursensitiver elektrischer Parameter (TSEP) untersucht und zur Temperaturbestimmung empfohlen wird. Für Gate Injection Transistors (GIT) wird ein ähnlicher Ansatz verfolgt. Aufgrund der Gatestruktur dieser stromgesteuerten Bauelemente wird vorgeschlagen, den vorhandenen pn-Übergang am Gate des GIT HEMT unter Verwendung der Gate-Source-Spannung als TSEP zu nutzen. In beiden Fällen erreichen die temperatursensitiven Parameter eine Messauflösung, die
mindestens der des pn-Übergangs bei Si-Bauelementen entspricht.
Im Lastwechseltest bestimmt im Wesentlichen die verwendete Aufbau- und Verbindungstechnik außerhalb des diskreten Packages die mögliche Zyklenzahl. Werden SMD-Bauelemente auf PCB gelötet, dominiert die Lotverbindung zwischen Bauteil und PCB den Ausfall. Durch ein neues Aufbaukonzept mit in Module gesinterten AlGaN/GaN Packages sind Zyklenzahlen möglich, die bis Faktor 10 über dem Erwartungswert für vergleichbare Si-Bauelemente mit Standard AVT liegen
GaN HEMT technology for W-band frequency applications
Owing to the technological advancement, and rapid industrial growth which stimulate a rapidly growing demand for more efficient transistor devices for high-power high-frequency applications, gallium nitride (GaN) material has been one of the most intensively researched semiconductor materials in the past two decades. Apart from its exceptional material properties, GaN exhibits a unique attribute of an ability to generate a sheet of high density highly mobile two dimensional electron gas (2DEG) without the need of any intentional doping. Due to the high mobility (~2000 cm2/V.s) and concentration (1X1013 cm-2) of the 2DEG, and the large energy band gap (3.4 eV), gallium nitride devices can efficiently deliver high-power at high operating frequencies. Its low intrinsic carrier density (~10-12/cm3) enables operating GaN devices at much high operating temperatures than other conventional semiconductor materials.
Despite this propound potential, due to some critical performance and reliability challenges, GaN transistors are yet to meet an acceptable industrial performance which leads to still limited deployment in the semiconductor market for electronic applications. The focus of this project is to improve in the device processing technology which has been one of the major causes of poor performance of GaN devices in high-power high-frequency applications. GaN devices suffer from high ohmic contact resistance, gate-to-source capacitance CGS, and inefficient heat dissipation property which severely results in high power losses, low efficiency, and low cutoff frequency. These affects the output power and high-frequency parameters (such as the unit power gain fmax and unit current gain ft cut-off frequencies). The conventional method of realising low ohmic contact using heavily doped GaN contact layer requires complex and time-consuming regrowth processes. In this work, we present a new approach of realising low ohmic contacts using the heavily doped GaN cap layer technique, but without regrowth. Instead of using the usual undoped 2 nm GaN cap layer, the approach involves growing a heavily doped 5 nm GaN cap layer with a Si-doping density of 1x1019 cm3 on the AlN/GaN HEMT using molecular beam epitaxy (MBE). This technique is cost effective and minimises complexity and processing time. We obtain a very low ohmic contact resistance of 0.132 Ω.mm with 428 Ω/sq sheet resistance, for AlN (aluminium nitride) barrier GaN high electron mobility transistors (HEMTs).
Reduction of gate length is required to realise a high-frequency device. However, such reduction results in high gate resistance which affects the maximum cut-off frequency of the device. A T-shape structure of gate is normally used to reduce the gate resistance. Because of the need of very small gate lengths in high-frequency devices, any further reduction of the gate length to sub-100 nm, could lead to a severe instability due to weakening mechanical strength of the gate structure. This has become a serious reliability concern, and consequently the T-shape gate is conventionally supported using thick passivation layer of dielectric materials such as Si3N4. This layer in turn results in an unwanted parasitic capacitance which affect the frequency performance of the device. In this work, we present a new fabrication technique which yields a robust and stable T-shape gate structure without the use of any supporting insulator such as Si3N4. While this approach has not been tested on a full wafer (>4 inches) yet, it shows promising potential for using it in commercial manufacturing.
In another strand of the research, we have demonstrated the benefit of AlGaN/GaN HEMTs on diamond as efficient heat extraction mechanism for GaN devices by using three identical AlGaN/GaN on diamond wafers with varying thicknesses of GaN buffer and the diamond substrates. Due to the efficient heat extraction property, a transistor with high power density, effective unity power gain and current-gain cut-off frequencies of 32.04 W/mm at VGS = 0 V and VDS = 60 V, 90 GHz and 128 GHz are realised, respectively. We analysed the impact of the buffer and substrate thicknesses and found that self-heating of the device is less in devices with thinner diamond substrate and even lesser when the buffer is thinner
Vertical III-V Nanowire Transistors for Low-Power Logic and Reconfigurable Applications
With rapid increase in energy consumption of electronics used in our daily life, the building blocks — transistors — need to work in a way that has high energy efficiency and functional density to meet the demand of further scaling. III-V channel combined with vertical nanowire gate-all-around (GAA) device architecture is a promising alternative to conventional Si transistors due to its excellent electrical properties in the channel and electrostatic control across the gate oxide in addition to reduced footprint. Based on this platform, two major objectives of this thesis are included: 1) to improve the performance of III-V p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) and tunnel FETs (TFETs) for low-power digital applications; 2) to integrate HfO2-based ferroelectric gate onto III-V FETs (FeFETs) and TFETs (ferro-TFETs) to enable reconfigurable operation for high functional density.The key bottleneck for all-III-V CMOS is its p-type MOSFETs (p-FETs) which are mainly made of GaSb or InGaSb. Rich surface states of III-Sb materials not only lead to decreased effective channel mobility due to more scattering, but also deteriorate the electrostatics. In this thesis, several approaches to improve p-FET performance have been explored. One strategy is to enhance the hole mobility by introducing compressive strain into III-Sb channel. For the first time, a high and uniform compressive strain near 1% along the transport direction has been achieved in downscaled GaSb nanowires by growing and engineering GaSb-GaAsSb core-shell structure, aiming for potential hole mobility enhancement. In addition, surface passivation using digital etch has been developed to improve the electrostatics with subthreshold swing (SS) down to 107 mV/dec. Moreover, the on-state performance including on-current (Ion) and transconductance (gm) have been enhanced by ∼50% using annealing with H2-based forming gas. Lastly, a novel p-FET structure with (In)GaAsSb channel has been developed and further improved off-state performance with SS = 71 mV/dec, which is the lowest value among all reported III-V p-FETs.Despite subthermionic operation, TFETs usually suffer from low drive current as well as the current operating below 60 mV/dec (I60). The second focus of this thesis is to fine-tune the InAs/(In)GaAsSb heterostructure tunnel junction and the doping in the source segment during epitaxy. As a result, a substantially increased I60 (>1 µA/µm) and Ion up to 40 µA/µm at source-drain bias of 0.5 V have been achieved, reaching a record compared to other reported TFETs.Finally, emerging ferroelectric oxide based on Zr-doped HfO2 (HZO) has been successfully integrated onto III-V vertical nanowire transistors to form FeFETs and ferro-TFETs with GAA architecture. The corresponding electrical performance and reliability have been carefully characterized with both DC and pulsed I-V measurements. The unique band-to-band tunneling in InAs/(In)GaAsSb/GaSb heterostructure TFET creates an ultrashort effective channel, leading to detection of localized potential variation induced by single domains and defects in nanoscale ferroelectric HZO without physical gate-length scaling. By introducing gate/source overlap structure in the ferro-TFET, non-volatile reconfigurable signal modulation with multiple modes including signal transmission, phase shift, frequency doubling, and mixing has been achieved in a single device with low drive voltage and only ∼0.01 µm2 footprint, thus increasing both functional density andenergy efficiency
Nanoscale Ferroic Materials—Ferroelectric, Piezoelectric, Magnetic, and Multiferroic Materials
Ferroic materials, including ferroelectric, piezoelectric, magnetic, and multiferroic materials, are receiving great scientific attention due to their rich physical properties. They have shown their great advantages in diverse fields of application, such as information storage, sensor/actuator/transducers, energy harvesters/storage, and even environmental pollution control. At present, ferroic nanostructures have been widely acknowledged to advance and improve currently existing electronic devices as well as to develop future ones. This Special Issue covers the characterization of crystal and microstructure, the design and tailoring of ferro/piezo/dielectric, magnetic, and multiferroic properties, and the presentation of related applications. These papers present various kinds of nanomaterials, such as ferroelectric/piezoelectric thin films, dielectric storage thin film, dielectric gate layer, and magnonic metamaterials. These nanomaterials are expected to have applications in ferroelectric non-volatile memory, ferroelectric tunneling junction memory, energy-storage pulsed-power capacitors, metal oxide semiconductor field-effect-transistor devices, humidity sensors, environmental pollutant remediation, and spin-wave devices. The purpose of this Special Issue is to communicate the recent developments in research on nanoscale ferroic materials
Infrared Photodetectors based on InSb and InAs Nanostructures via Heterogeneous Integration-Rapid Melt Growth and Template Assisted Selective Epitaxy
Monolithic heterogeneous integration of III-V semiconductors with the contemporary Si Complementary Metal Oxide Semiconductor (CMOS) technology has instigated a wide range of possibilities and functionalities in the semiconductor industry, in the field of digitalcircuits, optical sensors, light emitters, and high-frequency communication devices. However, the integration of III-V semiconductorsis not trivial due to the differences in lattice parameters, polarity, and thermal expansion coefficient. This thesis explores two integrationtechniques to form III-V nanostructures with potential applications in the infrared detection field.The first technique implemented in this thesis work is the Rapid Melt Growth technique. InSb, which has a large lattice mismatch(19%) to Si, is used to demonstrate the RMG integration technique. A flash lamp with a millisecond annealing technique is utilized tomelt and recrystallize amorphous InSb material to form a single crystalline material. The development of the fabrication process andthe experimental results for obtaining a single crystalline InSb-on-insulator from a Si seed area through the RMG process are presented.Electron Back Scatter Diffraction (EBSD) technique was employed to understand the crystal quality, orientation, and defects in theRMG InSb nanostructures. The InSb nanostructures have a resistivity of 10 mΩ cm, similar to the VLS-grown InSb nanowires.Mobility ranging from 3490 - 877 cm2/ V sec was extracted through Hall and Van der Pauw measurements. Finally, we report the firstmonolithic integrated InSb nanostructure photodetector on Si through the RMG process. Detailed optical and electrical characterizationof the device, including the spectrally resolved photocurrent and the temperature-dependent dark current, is studied. The thesis presentsan InSb photodetector with a stable photodetector with a responsivity of 0.5 A/W at 16 nW illumination and millisecond time response.The second integration technique implemented in this thesis work is Template Assisted Selective Epitaxy. Here, the versatility ofTASE technique to integrate InAs nanowires on W metal seed is demonstrated. This technique enables the feasibility of integratingIII-V semiconductors to back -end of the line integration with Si CMOS technology. EBSD technique was utilized to study andobtain the statistics on the single crystalline InAs nanowires grown from different diameter templates. We also demonstrate thepossibility of achieving an nBn InAs detector using TASE on W approach. This technique is a promising step towards developinghigh operating temperature (HOT) monolithic integrated mid-infrared detectors. Thus, the results of this thesis provide theperspective into two viable CMOS-compatible III-V integration techniques that could be utilized for photodetector applications at areduced cost
Monocrystalline Si/-GaO p-n heterojunction diodes fabricated via grafting
The -GaO has exceptional electronic properties with vast
potential in power and RF electronics. Despite the excellent demonstrations of
high-performance unipolar devices, the lack of p-type doping in
-GaO has hindered the development of GaO-based bipolar
devices. The approach of p-n diodes formed by polycrystalline p-type oxides
with n-type -GaO can face severe challenges in further advancing
the -GaO bipolar devices due to their unfavorable band alignment
and the poor p-type oxide crystal quality. In this work, we applied the
semiconductor grafting approach to fabricate monocrystalline
Si/-GaO p-n diodes for the first time. With enhanced
concentration of oxygen atoms at the interface of Si/-GaO,
double side surface passivation was achieved for both Si and
-GaO with an interface Dit value of 1-3 x 1012 /cm2 eV. A
Si/-GaO p-n diode array with high fabrication yield was
demonstrated along with a diode rectification of 1.3 x 107 at +/- 2 V, a diode
ideality factor of 1.13 and avalanche reverse breakdown characteristics. The
diodes C-V shows frequency dispersion-free characteristics from 10 kHz to 2
MHz. Our work has set the foundation toward future development of
-GaO-based transistors.Comment: 32 pages, 10 figures. The preliminary data were presented as a poster
in the 5th US Gallium Oxide Workshop, Washington, DC. August 07-10, 202
反応性力場分子動力学法および密度汎関数法による化学気相成長および原子層成長プロセスの解析
Tohoku University博士(工学)thesi
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