289 research outputs found
Feature Papers in Electronic Materials Section
This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book
Non-Silicon MOSFETs and Circuits with Atomic Layer Deposited Higher-k Dielectrics
The quest for technologies beyond 14nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on higher-k gate dielectrics integration with high mobility channel materials such as III-V semiconductors and germanium. Ternary oxides, such as La2-xYxO3 and LaAlO3, have been considered as strong candidates due to their high dielectric constants and good thermal stability. Meanwhile, the unique abilities of delivering large area uniform thin film, excellent controlling of composition and thickness to an atomic level, which are keys to ultra-scaled devices, have made atomic layer deposition (ALD) technique an excellent choice.
In this thesis, we systematically study the atomic layer epitaxy (ALE) process realized by ALD, ALE higher-k dielectric integration, GaAs nMOSFETs and pMOSFETs on (111)A substrates, and their related CMOS digital logic gate circuits as well as ring oscillators. A record high drain current of 376 mA/mm and a small SS of 74 mV/dec are obtained from planar GaAs nMOSFETs with 1μm gate length. La2-xYxO3/GaAs(111)A interfaces are systematically investigated in both material and electrical aspects. The work has expanded the near 50 years GaAs MOSFETs research to an unprecedented level. Following the GaAs work, Ge n- and p-MOSFETs with epitaxial interfaces are also fabricated and studied. Beyond the conventional semiconductors, the complex oxide channel material SrTiO3 is also explored. Well-behaved LaAlO3/SrTiO3 nMOSFETs with a conducting channel at insulating ALD amorphous LaAlO3 - insulating crystalline SrTiO3 interface are also demonstrated
Demonstration of High-Temperature Operation of Beta-Gallium Oxide (β-Ga2O3) Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET) with Electrostatic Model in COMSOL
β-Ga2O3 is a robust semiconductor material set with a large band gap of ~4.8 eV, low intrinsic carrier concentration, and high melting point that offers a stable platform for operating electronic devices at high temperatures and extreme environments. The first half of this thesis will cover the fabrication of a fixture and packaging to test electronic components at high temperatures. Then it will highlight the characterization of β-Ga2O3 field effect transistors from room temperature (RT) up to 500 °C. The devices, fabricated with Ni/Au and Al2O3 gate metal-oxide-semiconductor (MOS), demonstrate stable operation up to 500 oC. The tested device shows no measured current degradation in the ID-VD characteristics up to 450 oC. Improvements to the drain current, ID within this temperature range are due to activation carriers from dopants/traps and the negative push in threshold voltage, VT. The device exhibits a drop in ID at 500 °C; however, device characteristics recover once the device returns to RT. Even after 20 hours of device operation at 500 °C, the device shows negligible degradation. Device characteristics such as gate leakage, ION/IOFF ratio, gm, Ron, and contact resistance show monotonic variation with temperature. The experimental results suggest that an optimized choice of metals and gate dielectrics β-Ga2O3 will provide a platform for device operation at high temperatures and extreme environments. The second half of the thesis focuses on creating an electrostatic model of a metal-oxide-semiconductor field effect transistor with COMSOL finite element analysis software to understand the physics behind semiconductor technology
Material and device aspects of semiconducting two-dimensional crystals
Two-dimensional (2D) crystals have attracted much attention in recent years due to their unique physical, chemical, and mechanical properties. Semiconducting 2D crystals with van der Waals structures, such as transition metal dichalcogenides, are considered promising candidates for future device applications, as many have large band gaps, high carrier mobilities, and enable devices with immunity to short channel effects in addition to compatibility with silicon CMOS processes.^ In this thesis, the fundamental device implications of using semiconducting 2D crystals are investigated. This includes: 1) the optimization of device fabrication processing for better device performance, 2) comparing the device physics in 2D semiconductors based transistors and silicon MOSFET, and 3) circuit-level integration of devices using 2D semiconductors. A direct atomic layer deposition process was developed and investigated on various 2D crystals which allowed for the development of 2D semiconductor transistors. N-type MoS2 transistors with top and back gates were fabricated. The device performance of MoS2transistors with various channel lengths down to 50 nm was studied. Metal contacts on MoS2 and other TMD materials were also studied. They showed a strong Fermi-level pinning at the metal MoS 2 interface. Device performance based on single layer CVD MoS2 channel was studied and the device on/off switching was revealed to be dominated by Schottky barriers at metal contacts. Finally, the transport properties and device performance of p-type phosphorene crystals were investigated. Semiconducting 2D crystals are very promising candidates for future electronic and optoelectronic device applications
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Advanced III-V MOSFET
As scaling of silicon-based CMOS devices approaches its end, there is an ever increasing interest in high mobility materials. Among potential candidates for future CMOS devices, III-V materials are the most promising option due to their superior carrier transport properties. Despite their attractive material properties, they face several critical challenges that need to be resolved. The main limitation in III-V MOSFETs is lack of a good native oxide. Recently, devices utilizing a gate stack formed with high-κ and metal gate electrode are being explored for EOT scaling. Compared to Si MOSFETs, the surfaces of III-V channel materials are prone to deteriorate, resulting in degradation threshold voltage control, subthreshold characteristics, and overall device performance. The purpose of this dissertation is to address improvement of surface characteristics of III-V materials, especially, InGaAs. First of all, beryllium oxide (BeO) is considered as interface passivation layer for InGaAs MOSFETs. In order to apply BeO onto InGaAs, the chemical and mechanical properties are first studied. Liquid BeO precursor is never used in ALD systems. The chemical properties of ALD BeO film are revealed from AES, XPS, NRA, RBS, and REELS. Using nano-indentation, the mechanical characteristics of ALD BeO are investigated. The second part of the study focuses on the application of ALD BeO to InGaAs MOSFETs. The surface channel MOSFET is employed to understand BeO dielectric with III-V channel. The quantum well (QW) structure is known to withstand InGaAs intrinsic material properties from a device point of view. ALD BeO is applied to QW InGaAs MOSFETs as an interface passivation layer below HfO2. The impact of ALD BeO application for interface passivation is presented using the improvement in device characteristics, for example, drive current (ION), low leakage current (IOFF), effective mobility (μeff), and interface trap density (Dit). The third and final part are about process research for InGaAs surface quality. III-V channel materials are inherent to create notorious native oxide that needs to be treated before the fabrication process. In order to protect pristine III-V surface, in-situ Ar treatment is studied and used before high-κ deposition. In addition, deuterium (D2) high-pressure annealing is considered to passivate III-V interface with high-κ. To demonstrate the efficacy of these treatment processes, InGaAs MOSCAPs are fabricated, and capacitance characteristics are analyzed and compared. The C-V hysteresis and multi-frequency C-V are measured, and the interface trap density (Dit) is extracted using the C-V result.Electrical and Computer Engineerin
Enhancement of hydrogen terminated diamond FET performance through integration of electron acceptor oxides
This work reports on the improvement to the performance of hydrogen terminated diamond field effect transistors (FETs) by replacing surface adsorbed atmospheric species with transition metal oxides MoO3 and V2O5, and the implementation of a pre-deposition vacuum anneal at 400°C which is required to maintain the stability of the doping within the devices.
MESFET structures incorporating a metal/H-diamond gate contact were observed to be irreversibly damaged by exposure to the 400°C pre deposition vacuum annealing prior to deposition of MoO3 or V2O5. Therefore preliminary investigation of devices including the MoO3 or V2O5 without pre annealing was carried out. An increase in maximum drain current of up to 50% was observed when comparing output characteristics before and after deposition of MoO3 or V2O5 without the 400°C pre anneal.
Following this, investigation of the inclusion of Al2O3 into the FET structure as a gate dielectric was explored in order to increase the thermal robustness of the gate and allow inclusion of the pre deposition vacuum annealing at 400°C. It was shown that FETs fabricated using Al2O3 as a gate dielectric maintained transistor operation after vacuum annealing at 400°C and deposition of 10nm of MoO3 or V2O5. FETs were characterized after exposure to atmospheric adsorbates, and after deposition of 10nm of MoO3 or V2O5 and pre deposition 400°C vacuum anneal. FETs with Al2O3 gate dielectric using V2O5 and pre deposition annealing showed an increase in drain current of up to 276%. The V2O5 FETs using Al2O3 as a gate dielectric showed maximum drain currents of -376mA/mm, extrinsic transconductances of 97mS/mm, and on resistances as low as 17Ω.mm. These are important parameters for assessing the performance of power FETs
III-V and 2D Devices: from MOSFETs to Steep-Slope Transistors
With silicon CMOS technology approaching the scaling limit, alternating channel materials and novel device structures have been extensively studied and attracted a lot of attention in solid-state device research. In this dissertation, solid-state electron devices for post-Si CMOS applications are explored including both new materials such as III-V and 2D materials and new device structures such as tunneling field-effect transistors and negative capacitance field-effect transistors. Multiple critical challenges in applying such new materials and new device structures are addressed and the key achievements in this dissertation are summarized as follows: 1) Development of fabrication process technology for ultra-scaled planar and 3D InGaAs MOSFETs. 2) Interface passivation by forming gas anneal on InGaAs gate-all-around MOSFETs. 3) Characterization methods for ultra-scaled MOSFETs, including a correction to subthreshold method and low frequency noise characterization in short channel devices. 4) Development of short channel InGaAs planar and 3D gate-allaround tunneling field-effect transistors. 5) Negative capacitance field-effect transistors with hysteresis-free and bi-directional sub-thermionic subthreshold slope and the integration with various channel materials such as InGaAs and MoS2
Miniaturized Transistors, Volume II
In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before
Record Maximum Oscillation Frequency in C-face Epitaxial Graphene Transistors
The maximum oscillation frequency (fmax) quantifies the practical upper bound
for useful circuit operation. We report here an fmax of 70 GHz in transistors
using epitaxial graphene grown on the C-face of SiC. This is a significant
improvement over Si-face epitaxial graphene used in the prior high frequency
transistor studies, exemplifying the superior electronics potential of C-face
epitaxial graphene. Careful transistor design using a high {\kappa} dielectric
T-gate and self-aligned contacts, further contributed to the record-breaking
fmax
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