An Integrated Subharmonic Coupled-Oscillator Scheme for a 60-GHz Phased-Array Transmitter

This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200–MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below 100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors’ knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process

Periodically Disturbed Oscillators

By controlling the timing of events and enabling the transmission of data over long distances, oscillators can be considered to generate the "heartbeat" of modern electronic systems. Their utility, however, is boosted significantly by their peculiar ability to synchronize to external signals that are themselves periodic in time. Although this fascinating phenomenon has been studied by scientists since the 1600s, models for describing this behavior have seen a disconnect between the rigorous, methodical approaches taken by mathematicians and the design-oriented, physically-based analyses carried out by engineers. While the analytical power of the former is often concealed by an inundation of abstract mathematical machinery, the accuracy and generality of the latter are constrained by the empirical nature of the ensuing derivations. We hope to bridge that gap here. In this thesis, a general theory of electrical oscillators under the influence of a periodic injection is developed from first principles. Our approach leads to a fundamental yet intuitive understanding of the process by which oscillators lock to a periodic injection, as well as what happens when synchronization fails and the oscillator is instead injection pulled. By considering the autonomous and periodically time-varying nature that underlies all oscillators, we build a time-synchronous model that is valid for oscillators of any topology and periodic disturbances of any shape. A single first-order differential equation is shown to be capable of making accurate, quantitative predictions about a wide array of properties of periodically disturbed oscillators: the range of injection frequencies for which synchronization occurs, the phase difference between the injection and the oscillator under lock, stable vs. unstable modes of locking, the pull-in process toward lock, the dynamics of injection pulling, as well as phase noise in both free-running and injection-locked oscillators. The framework also naturally accommodates superharmonic injection-locked frequency division, subharmonic injection-locked frequency multiplication, and the general case of an arbitrary rational relationship between the injection and oscillation frequencies. A number of novel insights for improving the performance of systems that utilize injection locking are also elucidated. In particular, we explore how both the injection waveform and the oscillator's design can be modified to optimize the lock range. The resultant design techniques are employed in the implementation of a dual-moduli prescaler for frequency synthesis applications which features low power consumption, a wide operating range, and a small chip area. For the commonly used inductor-capacitor (LC) oscillator, we make a simple modification to our framework that takes the oscillation amplitude into account, greatly enhancing the model's accuracy for large injections. The augmented theory uniquely captures the asymmetry of the lock range as well as the distinct characteristics exhibited by different types of LC oscillators. Existing injection locking and pulling theories in the available literature are subsumed as special cases of our model. It is important to note that even though the veracity of our theoretical predictions degrades as the size of the injection grows due to our framework's linearization with respect to the disturbance, our model's validity across a broad range of practical injection strengths are borne out by simulations and measurements on a diverse collection of integrated LC, ring, and relaxation oscillators. Lastly, we also present a phasor-based analysis of LC and ring oscillators which yields a novel perspective into how the injection current interacts with the oscillator's core nonlinearity to facilitate injection locking.</p

Design of Frequency divider with voltage vontrolled oscillator for 60 GHz low power phase-locked loops in 65 nm RF CMOS

Increasing memory capacity in mobile devices, is driving the need of high-data rates equipment. The 7 GHz band around 60 GHz provides the opportunity for multi-gigabit/sec wireless communication. It is a real opportunity for developing next generation of High-Definition (HD) devices. In the last two decades there was a great proliferation of Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) topologies in RF ICs on silicon, but reaching high performance VCOs and FDs operating at 60 GHz is in today's technology a great challenge. A key reason is the inaccuracy of CMOS active and passive device models at mm-W. Three critical issues still constitute research objectives at 60 GHz in CMOS: generation of the Local Oscillator (LO) signal (1), division of the LO signal for the Phase-Locked Loop (PLL) closed loop (2) and distribution of the LO signal (3). In this Thesis, all those three critical issues are addressed and experimentally faced-up: a divide-by-2 FD for a PLL of a direct-conversion transceiver operating at mm-W frequencies in 65 nm RF CMOS technology has been designed. Critical issues such as Process, Voltage and Temperature (PVT) variations, Electromagnetic (EM) simulations and power consumption are addressed to select and design a FD with high frequency dividing range. A 60 GHz VCO is co-designed and integrated in the same die, in order to provide the FD with mm-W input signal. VCOs and FDs play critical roles in the PLL. Both of them constitute the PLL core components and they would need co-design, having a big impact in the overall performance especially because they work at the highest frequency in the PLL. Injection Locking FD (ILFD) has been chosen as the optimum FD topology to be inserted in the control loop of mm-W PLL for direct-conversion transceiver, due to the high speed requirements and the power consumption constraint. The drawback of such topology is the limited bandwidth, resulting in narrow Locking Range (LR) for WirelessHDTM applications considering the impact of PVT variations. A simulation methodology is presented in order to analyze the ILFD locking state, proposing a first divide-by-2 ILFD design with continuous tuning. In order to design a wide LR, low power consumption ILFD, the impacts of various alternatives of low/high Q tank and injection scheme are deeply analysed, since the ILFD locking range depends on the Q of the tank and injection efficiency. The proposed 3-bit dual-mixing 60 GHz divide-by-2 LC-ILFD is designed with an accumulation of switching varactors binary scaled to compensate PVT variations. It is integrated in the same die with a 4-bit 60 GHz LC-VCO. The overall circuit is designed to allow measurements of the singles blocks stand-alone and working together. The co-layout is carried on with the EM modelling process of passives devices, parasitics and transmission lines extracted from the layout. The inductors models provided by the foundry are qualified up to 40 GHz, therefore the EM analysis is a must for post-layout simulation. The PVT variations have been simulated before manufacturing and, based on the results achieved, a PLL scheme PVT robust, considering frequency calibration, has been patented. The test chip has been measured in the CEA-Leti (Grenoble) during a stay of one week. The operation principle and the optimization trade-offs among power consumption, and locking ranges of the final selected ILFD topology have been demonstrated. Even if the experimental results are not completely in agreement with the simulations, due to modelling error and inaccuracy, the proposed technique has been validated with post-measurement simulations. As demonstrated, the locking range of a low-power, discrete tuned divide-by-2 ILFD can be enhanced by increasing the injection efficiency, without the drawbacks of higher power consumption and chip area. A 4-bits wide tuning range LC-VCO for mm-W applications has been co-designed using the selected 65 nm CMOS process.Postprint (published version