Gate oxide failure in MOS devices

The thesis presents an experimental and theoretical investigation of gate oxide breakdown in MOS networks, with a particular emphasis on constant voltage overstress failure. It begins with a literature search on gate oxide failure mechanisms, particularly time-dependent dielectric breakdown, in MOS devices. The experimental procedure is then reported for the study of gate oxide breakdown under constant voltage stress. The experiments were carried out on MOSFETs and MOS capacitor structures, recording the characteristics of the devices before and after the stress. The effects of gate oxide breakdown in one of the transistors in an nMOS inverter were investigated and several parameters were found to have changed. A mathematical model for oxide breakdown, based on physical mechanisms, is proposed. Both electron and hole trapping occurred during the constant voltage stress. Breakdown appears to take place when the trapped hole density reach a critical value. PSPICE simulations were performed for the MOSFETs, nMOS inverter and CMOS logic circuits. Two models of MOSFET with gate oxide short were validated. A good agreement between experiments and simulations was achieved

Electrical overstress and electrostatic discharge failure in silicon MOS devices

This thesis presents an experimental and theoretical investigation of electrical failure in MOS structures, with a particular emphasis on short-pulse and ESD failure. It begins with an extensive survey of MOS technology, its failure mechanisms and protection schemes. A program of experimental research on MOS breakdown is then reported, the results of which are used to develop a model of breakdown across a wide spectrum of time scales. This model, in which bulk-oxide electron trapping/emission plays a major role, prohibits the direct use of causal theory over short time-scales, invalidating earlier theories on the subject. The work is extended to ESD stress of both polarities. Negative polarity ESD breakdownis found to be primarily oxide-voltage activated, with no significant dependence on temperature of luminosity. Positive polarity breakdown depends on the rate of surface inversion, dictated by the Si avalanche threshold and/or the generation speed of light-induced carriers. An analytical model, based upon the above theory is developed to predict ESD breakdown over a wide range of conditions. The thesis ends with an experimental and theoretical investigation of the effects of ESD breakdown on device and circuit performance. Breakdown sites are modelled as resistive paths in the oxide, and their distorting effects upon transistor performance are studied. The degradation of a damaged transistor under working stress is observed, giving a deeper insight into the latent hazards of ESD damage

ELECTROSTATIC DISCHARGE AND ELECTRICAL OVERSTRESS FAILURES OF NON-SILICON DEVICES

Electrostatic discharge (ESD) causes a significant percentage of the failures in the electronics industry. The shrinking size of semiconductor circuits, thinner gate oxides, complex chips with multiple power supplies and mixed-signal blocks, larger chip capacitance and faster circuit operation, all contribute to increased ESD sensitivity of advanced semiconductor devices. Therefore, understanding and controlling ESD is indispensable for higher quality and reliability of advanced device technologies. This thesis provides a comprehensive understanding of ESD and EOS failures in GaAs and SiGe devices. In the first part of this thesis, characteristics of internal damage caused by several ESD test models and EOS stress in non-silicon devices (GaAs and SiGe) are identified. Failure signatures are correlated with field failures using various failure analysis techniques. The second part of this thesis discusses the effects of ESD latent damage in GaAs devices. Depending on the stress level, ESD voltage can causes latent failures if the device is repeatedly stressed under low ESD voltage conditions, and can cause premature damage leading eventually to catastrophic failures. Electrical degradation due to ESD-induced latent damage in GaAs MESFETs after cumulative low-level ESD stress is studied. Using failure analysis, combined with electrical characterization, the failure modes and signatures of EOS stressed devices with and without prior low-level ESD stress are compared. To predict the power-to-failure level of GaAs and silicon devices, an ESD failure model using a thermal RC network was developed. A correlation method of the real ESD stress and square wave pulse has been developed. The equivalent duration of the square pulse is calculated and proposed for the HBM ESD stress. The dependence of this value on the ESD stress level and material properties is presented as well

High-Voltage Integrated Circuits design and validation for automotive applications

Electronic Integrated Circuits (ICs) are an important pillar of the automotive market, especially since legal and safety requirements have been introduced to manage vehicles emissions and behaviors. Furthermore, the harsh environment and the tight safety requirements, summed with the market that is pushing to reduce the development lead time and to increase the system complexity, require to develop dedicated ICs for the automotive applications. This thesis presents some peculiar high-power and high-voltage ICs for automotive applications that have been studied, designed and developed taking into account all the requirements that automotive grade ICs have to respect, with emphasis on performance, quality and safety aspects. Particularly the thesis reports the design and validation of power management blocks and output drivers for inductive loads, showing how to fulfill in an effective way the performance, quality and safety targets according to the guidelines and the constraints of the latest automotive standards, like ISO26262 and AEC-Q100. All the designed ICs has been simulated and manufactured, including layout drawings, in a 0.35um HV-CMOS technology from AMS. The effectiveness and robustness of the proposed circuits has been validated on silicon and corresponded measurement results has been reported

Guidelines for Verification Strategies to Minimize RISK Based on Mission Environment, -Application and -Lifetime (MEAL)

There is a trend of compromising verification testing to address the cost and schedule constraints, which poses a high-risk posture for programs/projects. Current and emerging aerospace scientific and/or human exploration programs continue to pose new technological challenges. These technological challenges combined with finite budgets and truncated schedules are forcing designers, scientists, engineers, and managers to push technologies to their physical limits. In addition, budget and schedule pressures challenge how those technologies/missions are verified. A clear understanding of the different verification processes is needed to ensure the proper verification of the technology within the mission (i.e., capabilities, advantages, and limitations). The goal of verification is to prove through test, analysis, inspection, and/or demonstration that a product provides its required function while meeting the performance requirements. It is important that verification yield understanding of representative performance under worst-case conditions so that margins to failure can be evaluated for proposed applications. The capabilities, advantages, and limitations of the testing and inspection performed at each level are different, and the risk incurred by omitting a verification step depends on the level of integration as well as Mission, Environment, Application and Lifetime (MEAL). This paper focuses on verification processes. The goal of the verification process is to ensure the given avionics technology could be safely implemented on the given MEAL consistent with the program/project risk posture

H2 Safety in Human Operations – and Safety guideline

publishedVersio

Electrostatic Discharge

As we enter the nanoelectronics era, electrostatic discharge (ESD) phenomena is an important issue for everything from micro-electronics to nanostructures. This book provides insight into the operation and design of micro-gaps and nanogenerators with chapters on low capacitance ESD design in advanced technologies, electrical breakdown in micro-gaps, nanogenerators from ESD, and theoretical prediction and optimization of triboelectric nanogenerators. The information contained herein will prove useful for for engineers and scientists that have an interest in ESD physics and design