13 research outputs found
Low-Power SAR ADCs:Basic Techniques and Trends
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples
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Design and implementation of Radix-3/Radix-2 based novel hybrid SAR ADC in scaled CMOS technologies
This thesis focuses on low power and high speed design techniques for successive
approximation register (SAR) analog-to-digital converters (ADCs) in nanoscale
CMOS technologies. SAR ADCs’ speed is limited by the number of bits of
resolution. An N-bit conventional SAR ADC takes N conversion cycles. To speed
up the conversion process, we introduce a radix-3 SAR ADC which can compute
1:6 bits per cycle. To our knowledge, it is the first fully programmable and efficiently
hardware controlled radix-3 SAR ADC. We had to use two comparators per
cycle due to ADC architecture and we proposed a simple calibration scheme for
the comparators. Also, as the architecture of the DAC array is completely different
from the architecture of conventional radix-2 SAR ADC’s DAC arrays, we came up
with an algorithm for calibration of capacitors of the DAC.
Low power SAR ADCs face two major challenges especially at high resolutions:
(1) increased comparator power to suppress the noise, and (2) increased
DAC switching energy due to the large DAC size. Due to our proposed architecture,the radix-3 SAR ADC uses two comparators per cycle and two differential DACs.
To improve the comparator’s power efficiency, an efficient and low cost calibration
technique has been introduced. It allows a low power and noisy comparator to
achieve high signal-to-noise ratio (SNR).
To improve the DAC switching energy, we introduced a radix-3/radix-2
based novel hybrid SAR ADC. We use two single ended DACs for radix-3 SAR
ADC and these two single ended DACs can be used as one differential DAC for
radix-2 SAR ADC. So, overall, we only have a single DAC as conventional radix-
2 SAR ADC. In addition, a monotonic switching technique is adopted for radix-2
search to reduce the DAC capacitor size and hence, to reduce switching power. It
can reduce the total number of unit capacitors by four times. Our proposed hybrid
SAR ADC can achieve less DAC energy compared to radix-3 and radix-2 SAR
ADCs. Also, to utilize technology scaling, we used the minimum capacitor size
allowed by thermal noise limitations. To achieve high resolution, we introduced
calibration algorithm for the DAC array.
As mentioned earlier, the radix-3 SAR ADC offers higher power than conventional
radix-2 SAR ADC because of simultaneous use of two comparators. In
the proposed hybrid SAR ADC, we will be using radix-3 search for first few MSB
bits. So, the resolution required for radix-3 comparators are much larger than the
LSB value of 10-bit ADC. By implementing calibration of comparators, we can
use low power, high input referred offset and high speed comparators for radix-3
search. Radix-2 search will be used for rest of the bits and the resolution of the
radix-2 comparator has to be less than the required LSB value. So, a high power, low input referred offset and high speed comparator is used for radix-2 search.
Also, we introduced clock gating for comparators. So, radix-3 comparators will not
toggle during radix-2 search and the radix-2 comparators will be inactive during
radix-3 search. By using the aforementioned techniques, the overall comparator
power is definitely less than a radix-3 SAR ADC and comparable to a conventional
radix-2 SAR ADC.
A prototype radix-3/radix-2 based hybrid SAR ADC with the proposed
technique is designed and fabricated in 40nm CMOS technology. It achieves an
SNDR of 56.9 dB and consumes only 0.38 mW power at 30MS/s, leading to a
Walden figure of merit of 21.5 fJ/conv-step.Electrical and Computer Engineerin
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Design Techniques for High-Performance SAR A/D Converters
The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs.
ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption.
Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s.
The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew
calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology
Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs
This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account.
In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected.
The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration
Analysis, modeling and design of Successive Approach Analog-Digital Converters (SARADCs) with Digital Redundancy
Universidad de Sevilla. Máster Universitario en Microelectrónica: Diseño y Aplicaciones de Sistemas Micro/Nanométrico
DESIGN OF LOW-POWER LOW-VOLTAGE SUCCESSIVE-APPROXIMATION ANALOG-TO-DIGITAL CONVERTERS
Ph.DDOCTOR OF PHILOSOPH
Wideband CMOS Data Converters for Linear and Efficient mmWave Transmitters
With continuously increasing demands for wireless connectivity, higher\ua0carrier frequencies and wider bandwidths are explored. To overcome a limited transmit power at these higher carrier frequencies, multiple\ua0input multiple output (MIMO) systems, with a large number of transmitters\ua0and antennas, are used to direct the transmitted power towards\ua0the user. With a large transmitter count, each individual transmitter\ua0needs to be small and allow for tight integration with digital circuits. In\ua0addition, modern communication standards require linear transmitters,\ua0making linearity an important factor in the transmitter design.In this thesis, radio frequency digital-to-analog converter (RF-DAC)-based transmitters are explored. They shift the transition from digital\ua0to analog closer to the antennas, performing both digital-to-analog\ua0conversion and up-conversion in a single block. To reduce the need for\ua0computationally costly digital predistortion (DPD), a linear and wellbehaved\ua0RF-DAC transfer characteristic is desirable. The combination\ua0of non-overlapping local oscillator (LO) signals and an expanding segmented\ua0non-linear RF-DAC scaling is evaluated as a way to linearize\ua0the transmitter. This linearization concept has been studied both for\ua0the linearization of the RF-DAC itself and for the joint linearization of\ua0the cascaded RF-DAC-based modulator and power amplifier (PA) combination.\ua0To adapt the linearization, observation receivers are needed.\ua0In these, high-speed analog-to-digital converters (ADCs) have a central\ua0role. A high-speed ADC has been designed and evaluated to understand\ua0how concepts used to increase the sample rate affect the dynamic performance
CMOS Data Converters for Closed-Loop mmWave Transmitters
With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2
76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations
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Time and statistical information utilization in high efficiency sub-micron CMOS successive approximation analog to digital converters
In an industrial and consumer electronic marketplace that is increasingly demanding greater real-world interactivity in portable and distributed devices, analog to digital converter efficiency and performance is being carefully examined. The successive approximation (SAR) analog to digital converter (ADC) architecture has become popular for its high efficiency at mid-speed and resolution requirements. This is due to the one core single bit quantizer, lack of residue amplification, and large digital domain processing allowing for easy process scaling. This work examines the traditional binary capacitive SAR ADC time and statistical information and proposes new structures that optimize ADC performance. The Ternary SAR (TSAR) uses the quantizer delay information to enhance accuracy, speed and power consumption of the overall SAR while providing multi-level redundancy. The early reset merged capacitor switching SAR (EMCS) identifies lost information in the SAR subtraction and optimizes a full binary quanitzer structure for a Ternary MCS DAC. Residue Shaping is demonstrated in SAR and pipeline configurations to allow for an extra bit of signal to noise quantization ratio (SQNR) due to multi-level redundancy. The feedback initialized ternary SAR (FITSAR) is proposed which splits a TSAR into separate binary and ternary sub-ADC structures for speed and power benefits with an inter-stage encoding that not only maintains residue shaping across the binary SAR, but allows for nearly optimally minimal energy consumption for capacitive ternary DACs. Finally, the ternary SAR ideas are applied to R2R DACs to reduce power consumption. These ideas are tested both in simulation and with prototype results
Analog and Mixed Signal Design towards a Miniaturized Sleep Apnea Monitoring Device
Sleep apnea is a sleep-induced breathing disorder with symptoms of momentary and often repetitive cessations in breathing rhythm or sustained reductions in breathing amplitude. The phenomenon is known to occur with varying degrees of severity in literally millions of people around the world and cause a range of chronicle health issues. In spite of its high prevalence and serious consequences, nearly 80% of people with sleep apnea condition remain undiagnosed. The current standard diagnosis technique, termed polysomnography or PSG, requires the patient to schedule and undergo a complex full-night sleep study in a specially-equipped sleep lab. Due to both high cost and substantial inconvenience, millions of apnea patients are still undiagnosed and thus untreated. This research work aims at a simple, reliable, and miniaturized solution for in-home sleep apnea
diagnosis purposes. The proposed solution bears high-level integration and minimal interference with sleeping patients, allowing them to monitor their apnea conditions at the comfort of their homes.
Based on a MEMS sensor and an effective apnea detection algorithm, a low-cost single-channel apnea screening solution is proposed. A custom designed IC chip implements the apnea detection algorithm using time-domain signal processing techniques. The chip performs autonomous apnea detection and scoring based on the patient’s airflow signals detected by the MEMS sensor. Variable sensitivity is enabled to accommodate different breathing signal amplitudes. The IC chip was fabricated in standard 0.5-μm CMOS technology. A prototype device was designed and assembled including a MEMS sensor, the apnea detection IC chip, a PSoC platform, and wireless transceiver for data transmission. The prototype device demonstrates a valuable screening solution with great potential to reach the broader public with undiagnosed apnea conditions.
In a battery-operated miniaturized medical device, an energy-efficient analog-to-digital converter is an integral part linking the analog world of biomedical signals and the digital domain with powerful signal processing capabilities. This dissertation includes the detailed design of a successive approximation register (SAR) ADC for ultra-low power applications. The ADC adopts an asynchronous 2b/step scheme that halves both conversion time and DAC/digital circuit’s switching activities to reduce static and dynamic energy consumption. A low-power sleep mode is engaged at the end of all conversion steps during each clock period. The technical contributions of this ADC design include an innovative 2b/step reference scheme based on a hybrid R-2R/C-3C DAC, an interpolation-assisted
time-domain 2b comparison scheme, and a TDC with dual-edge-comparison mechanism. The prototype ADC was fabricated in 0.18μm CMOS process with an active area of 0.103 mm^(2), and achieves an ENoB of 9.2 bits and an FoM of 6.7 fJ/conversion-step at 100-kS/s