229 research outputs found
CMOS Hyperbolic Sine ELIN filters for low/audio frequency biomedical applications
Hyperbolic-Sine (Sinh) filters form a subclass of Externally-Linear-Internally-Non-
Linear (ELIN) systems. They can handle large-signals in a low power environment under half
the capacitor area required by the more popular ELIN Log-domain filters. Their inherent
class-AB nature stems from the odd property of the sinh function at the heart of their
companding operation. Despite this early realisation, the Sinh filtering paradigm has not
attracted the interest it deserves to date probably due to its mathematical and circuit-level
complexity.
This Thesis presents an overview of the CMOS weak inversion Sinh filtering
paradigm and explains how biomedical systems of low- to audio-frequency range could
benefit from it. Its dual scope is to: consolidate the theory behind the synthesis and design of
high order Sinh continuous–time filters and more importantly to confirm their micro-power
consumption and 100+ dB of DR through measured results presented for the first time.
Novel high order Sinh topologies are designed by means of a systematic
mathematical framework introduced. They employ a recently proposed CMOS Sinh
integrator comprising only p-type devices in its translinear loops. The performance of the
high order topologies is evaluated both solely and in comparison with their Log domain
counterparts. A 5th order Sinh Chebyshev low pass filter is compared head-to-head with a
corresponding and also novel Log domain class-AB topology, confirming that Sinh filters
constitute a solution of equally high DR (100+ dB) with half the capacitor area at the expense
of higher complexity and power consumption. The theoretical findings are validated by
means of measured results from an 8th order notch filter for 50/60Hz noise fabricated in a
0.35μm CMOS technology. Measured results confirm a DR of 102dB, a moderate SNR of
~60dB and 74μW power consumption from 2V power supply
An Efficient Parallel-in-Time Method for Optimization with Parabolic PDEs
To solve optimization problems with parabolic PDE constraints, often methods
working on the reduced objective functional are used. They are computationally
expensive due to the necessity of solving both the state equation and a
backward-in-time adjoint equation to evaluate the reduced gradient in each
iteration of the optimization method. In this study, we investigate the use of
the parallel-in-time method PFASST in the setting of PDE constrained
optimization. In order to develop an efficient fully time-parallel algorithm we
discuss different options for applying PFASST to adjoint gradient computation,
including the possibility of doing PFASST iterations on both the state and
adjoint equations simultaneously. We also explore the additional gains in
efficiency from reusing information from previous optimization iterations when
solving each equation. Numerical results for both a linear and a non-linear
reaction-diffusion optimal control problem demonstrate the parallel speedup and
efficiency of different approaches
Image compression and energy harvesting for energy constrained sensors
Title from PDF of title page, viewed on June 21, 2013Dissertation advisor: Walter D. Leon-SalasVitaIncludes bibliographic references (pages 176-[187])Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2013The advances in complementary metal-oxide-semiconductor (CMOS) technology
have led to the integration of all components of electronic system into a single integrated
circuit. Ultra-low power circuit techniques have reduced the power consumption of circuits.
Moreover, solar cells with improved efficiency can be integrated on chip to harvest
energy from sunlight. As a result of all the above, a new class of miniaturized electronic
systems known as self-powered system on a chip has emerged. There is an increasing research
interest in the area of self-powered devices which provide cost-effective solutions
especially when these devices are used in the areas that changing or replacing batteries is
too costly. Therefore, image compression and energy harvesting are studied in this dissertation.
The integration of energy harvesting, image compression, and an image sensor
on the same chip provides the energy source to charge a battery, reduces the data rate, and improves the performance of wireless image sensors. Integrated circuits of image compression,
solar energy harvesting, and image sensors are studied, designed, and analyzed
in this work. In this dissertation, a hybrid image sensor that can perform the tasks of sensing and
energy harvesting is presented. Photodiodes of hybrid image sensor can be programmed
as image sensors or energy harvesting cells. The hybrid image sensor can harvest energy
in between frames, in sleep mode, and even when it is taking images. When sensing
images and harvesting energy are both needed at the same time, some pixels have to
work as sensing pixels, and the others have to work as solar cells. Since some pixels are
devoted to harvest energy, the resolution of the image will be reduced. To preserve the
resolution or to keep the fair resolution when a lot of energy collection is needed, image
reconstruction algorithms and compressive sensing theory provide solutions to achieve
a good image quality. On the other hand, when the battery has enough charge, image
compression comes into the picture. Multiresolution decomposition image compression
provides a way to compress image data in order to reduce the energy need from data
transmission. The solution provided in this dissertation not only harvests energy but also
saves energy resulting long lasting wireless sensors. The problem was first studied at the system level to identify the best system-level
configuration which was then implemented on silicon. As a proof of concept, a 32 x 32 array of hybrid image sensor, a 32 x 32 array of image sensor with multiresolution decomposition compression, and a compressive sensing converter have been designed
and fabricated in a standard 0.5 [micrometer] CMOS process. Printed circuit broads also have been
designed to test and verify the proposed and fabricated chips. VHDL and Matlab codes
were written to generate the proper signals to control, and read out data from chips. Image
processing and recovery were carried out in Matlab. DC-DC converters were designed to
boost the inherently low voltage output of the photodiodes. The DC-DC converter has
also been improved to increase the efficiency of power transformation.Introduction -- Hybrid imager system and circuit design -- Hybrid imager energy harvesting and image acquisition results and discussion -- Detailed description and mathematical analysis for a circuit of energy harvesting using on-chip solar cells -- Multiresolution decomposition for lossless and near-lossless compression -- An incremental [sigma-delta] converter for compressive sensing -- Detailed description of a sigma-delta random demodulator converter architecture for compressive sensing applications -- Conclusion -- Appendix A. Chip pin-out -- Appendix B. Schematics -- Appendix C. Pictures of custom PC
Distributed video through telecommunication networks using fractal image compression techniques
The research presented in this thesis investigates the use of fractal compression techniques for a real time video distribution system. The motivation for this work was that the method has some useful properties which satisfy many requirements for video compression. In addition, as a novel technique, the fractal compression method has a great potential. In this thesis, we initially develop an understanding of the state of the art in image and video compression and describe the mathematical concepts and basic terminology of the fractal compression algorithm. Several schemes which aim to the improve of the algorithm, for still images are then examined. Amongst these, two novel contributions are described. The first is the partitioning of the image into sections which resulted insignificant reduction of the compression time. In the second, the use of the median metric as alternative to the RMS was considered but was not finally adopted, since the RMS proved to be a more efficient measure. The extension of the fractal compression algorithm from still images to image sequences is then examined and three different schemes to reduce the temporal redundancy of the video compression algorithm are described. The reduction in the execution time of the compression algorithm that can be obtained by the techniques described is significant although real time execution has not yet been achieved. Finally, the basic concepts of distributed programming and networks, as basic elements of a video distribution system, are presented and the hardware and software components of a fractal video distribution system are described. The implementation of the fractal compression algorithm on a TMS320C40 is also considered for speed benefits and it is found that a relatively large number of processors are needed for real time execution
Digital imaging technology assessment: Digital document storage project
An ongoing technical assessment and requirements definition project is examining the potential role of digital imaging technology at NASA's STI facility. The focus is on the basic components of imaging technology in today's marketplace as well as the components anticipated in the near future. Presented is a requirement specification for a prototype project, an initial examination of current image processing at the STI facility, and an initial summary of image processing projects at other sites. Operational imaging systems incorporate scanners, optical storage, high resolution monitors, processing nodes, magnetic storage, jukeboxes, specialized boards, optical character recognition gear, pixel addressable printers, communications, and complex software processes
Ultra low power wearable sleep diagnostic systems
Sleep disorders are studied using sleep study systems called Polysomnography that records several biophysical parameters during sleep. However, these are bulky and are typically located in a medical facility where patient monitoring is costly and quite inefficient. Home-based portable systems solve these problems to an extent but they record only a minimal number of channels due to limited battery life.
To surmount this, wearable sleep system are desired which need to be unobtrusive and have long battery life. In this thesis, a novel sleep system architecture is presented that enables the design of an ultra low power sleep diagnostic system. This architecture is capable of extending the recording time to 120 hours in a wearable system which is an order of magnitude improvement over commercial wearable systems that record for about 12 hours. This architecture has in effect reduced the average power consumption of 5-6 mW per channel to less than 500 uW per channel. This has been achieved by eliminating sampled data architecture, reducing the wireless transmission rate and by moving the sleep scoring to the sensors. Further, ultra low power instrumentation amplifiers have been designed to operate in weak inversion region to support this architecture.
A 40 dB chopper-stabilised low power instrumentation amplifiers to process EEG were designed and tested to operate from 1.0 V consuming just 3.1 uW for peak mode operation with DC servo loop. A 50 dB non-EEG amplifier continuous-time bandpass amplifier with a consumption of 400 nW was also fabricated and tested. Both the amplifiers achieved a high CMRR and impedance that are critical for wearable systems. Combining these amplifiers with the novel architecture enables the design of an ultra low power sleep recording system. This reduces the size of the battery required and hence enables a truly wearable system.Open Acces
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