Cluster-based architecture for fault-tolerant quantum computation

We present a detailed description of an architecture for fault-tolerant quantum computation, which is based on the cluster model of encoded qubits. In this cluster-based architecture, concatenated computation is implemented in a quite different way from the usual circuit-based architecture where physical gates are recursively replaced by logical gates with error-correction gadgets. Instead, some relevant cluster states, say fundamental clusters, are recursively constructed through verification and postselection in advance for the higher-level one-way computation, which namely provides error-precorrection of gate operations. A suitable code such as the Steane seven-qubit code is adopted for transversal operations. This concatenated construction of verified fundamental clusters has a simple transversal structure of logical errors, and achieves a high noise threshold ~ 3 % for computation by using appropriate verification procedures. Since the postselection is localized within each fundamental cluster with the help of deterministic bare controlled-Z gates without verification, divergence of resources is restrained, which reconciles postselection with scalability.Comment: 16 pages, 34 figure

A General Framework for Sound and Complete Floyd-Hoare Logics

This paper presents an abstraction of Hoare logic to traced symmetric monoidal categories, a very general framework for the theory of systems. Our abstraction is based on a traced monoidal functor from an arbitrary traced monoidal category into the category of pre-orders and monotone relations. We give several examples of how our theory generalises usual Hoare logics (partial correctness of while programs, partial correctness of pointer programs), and provide some case studies on how it can be used to develop new Hoare logics (run-time analysis of while programs and stream circuits).Comment: 27 page

On fault-tolerance with noisy and slow measurements

It is not so well-known that measurement-free quantum error correction protocols can be designed to achieve fault-tolerant quantum computing. Despite the potential advantages of using such protocols in terms of the relaxation of accuracy, speed and addressing requirements on the measurement process, they have usually been overlooked because they are expected to yield a very bad threshold as compared to error correction protocols which use measurements. Here we show that this is not the case. We design fault-tolerant circuits for the 9 qubit Bacon-Shor code and find a threshold for gates and preparation of $p_{(p,g) thresh}=3.76 \times 10^{-5}$ (30% of the best known result for the same code using measurement based error correction) while admitting up to 1/3 error rates for measurements and allocating no constraints on measurement speed. We further show that demanding gate error rates sufficiently below the threshold one can improve the preparation threshold to $p_{(p)thresh} = 1/3$. We also show how these techniques can be adapted to other Calderbank-Shor-Steane codes.Comment: 11 pages, 7 figures. v3 has an extended exposition and several simplifications that provide for an improved threshold value and resource overhea

Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers

Recent developments in engineering and algorithms have made real-world applications in quantum computing possible in the near future. Existing quantum programming languages and compilers use a quantum assembly language composed of 1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this quantum assembly to electric signals (called control pulses) that implement the specified computation on specific physical devices. However, there is a mismatch between the operations defined by the 1- and 2-qubit logical ISA and their underlying physical implementation, so the current practice of directly translating logical instructions into control pulses results in inefficient, high-latency programs. To address this inefficiency, we propose a universal quantum compilation methodology that aggregates multiple logical operations into larger units that manipulate up to 10 qubits at a time. Our methodology then optimizes these aggregates by (1) finding commutative intermediate operations that result in more efficient schedules and (2) creating custom control pulses optimized for the aggregate (instead of individual 1- and 2-qubit operations). Compared to the standard gate-based compilation, the proposed approach realizes a deeper vertical integration of high-level quantum software and low-level, physical quantum hardware. We evaluate our approach on important near-term quantum applications on simulations of superconducting quantum architectures. Our proposed approach provides a mean speedup of $5\times$, with a maximum of $10\times$. Because latency directly affects the feasibility of quantum computation, our results not only improve performance but also have the potential to enable quantum computation sooner than otherwise possible.Comment: 13 pages, to apper in ASPLO

Overview of Hydra: a concurrent language for synchronous digital circuit design

Hydra is a computer hardware description language that integrates several kinds of software tool (simulation, netlist generation and timing analysis) within a single circuit specification. The design language is inherently concurrent, and it offers black box abstraction and general design patterns that simplify the design of circuits with regular structure. Hydra specifications are concise, allowing the complete design of a computer system as a digital circuit within a few pages. This paper discusses the motivations behind Hydra, and illustrates the system with a significant portion of the design of a basic RISC processor

Fault-tolerant magic state preparation with flag qubits

Magic state distillation is one of the leading candidates for implementing universal fault-tolerant logical gates. However, the distillation circuits themselves are not fault-tolerant, so there is additional cost to first implement encoded Clifford gates with negligible error. In this paper we present a scheme to fault-tolerantly and directly prepare magic states using flag qubits. One of these schemes uses a single extra ancilla, even with noisy Clifford gates. We compare the physical qubit and gate cost of this scheme to the magic state distillation protocol of Meier, Eastin, and Knill, which is efficient and uses a small stabilizer circuit. In some regimes, we show that the overhead can be improved by several orders of magnitude.Comment: 26 pages, 17 figures, 5 tables. Comments welcome! v2 (published version): quantumarticle documentclass and expanded discussions on the fault-tolerant scheme