4,521 research outputs found

    Self-tuning run-time reconfigurable PID controller

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    Digital PID control algorithm is one of the most commonly used algorithms in the control systems area. This algorithm is very well known, it is simple, easily implementable in the computer control systems and most of all its operation is very predictable. Thus PID control has got well known impact on the control system behavior. However, in its simple form the controller have no reconfiguration support. In a case of the controlled system substantial changes (or the whole control environment, in the wider aspect, for example if the disturbances characteristics would change) it is not possible to make the PID controller robust enough. In this paper a new structure of digital PID controller is proposed, where the policy-based computing is used to equip the controller with the ability to adjust it's behavior according to the environmental changes. Application to the electro-oil evaporator which is a part of distillation installation is used to show the new controller structure in operation

    Structured Mapping of Petri Net States and Events for FPGA Implementations

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    The paper presents a new method of structured encoding of global internal states and events in Reconfigurable Logic Controllers, which are directly mapped into Field Programmable Gate Arrays (FPGA). Modular, concurrently decomposed, colored state machine is chosen as a intermediate model, before the mapping of Petri net into an array structure of dedicated but very flexible and reliable digital system. The initial textual specification in formal Gentzen logic serves both as a design description for a rapid prototyping, as well as formal model, suitable for detailed computer-based reasoning about optimized and synthesized logic controller, implemented in configurable hardware. Only the selected linear subset from general, universal propositional Gentzen Logic is necessary to deduce several properties of the net, such as relations of nonconcurrency among structurally ordered macroplaces. The goal of this paper is to present the design methodology for modeling and synthesis of discrete controllers using related Petri net theory, rule-based theory (mathematical logic), and VHDL

    Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

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    This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

    Partial Reconfiguration in the Field of Logic Controllers Design

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    The paper presents method for logic controllers multi context implementation by means of partial reconfiguration. The UML state machine diagram specifies the behaviour of the logic controller. Multi context functionality is specified at the specification level as variants of the composite state. Each composite state, both orthogonal or compositional, describes specific functional requirement of the control process. The functional decomposition provided by composite states is required by the dynamic partial reconfiguration flow. The state machines specified by UML state machine diagrams are transformed into hierarchical configurable Petri nets (HCfgPN). HCfgPN are a Petri nets variant with the direct support of the exceptions handling mechanism. The paper presents placesoriented method for HCfgPN description in Verilog language. In the paper proposed methodology was illustrated by means of simple industrial control process
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