A FPGA/DSP design for real-time fracture detection using low transient pulse

This work presents the hardware and software architecture for the detection of fractures and edges in materials. While the detection method is based on the novel concept of Low Transient Pulse (LTP), the overall system implementation is based on two digital microelectronics technologies widely used for signal processing: Digital Signal Processor (DSP) and Field Programmable Gate Array (FPGA). Under the proposed architecture, the DSP carries out the analysis of the received baseband signal at a lower rate and hence can be used for large number of signal channels. The FPGA\u27s master clock runs at a higher frequency (62.5MHz) for the generation of LTP signal and to demodulate the passband ultrasonic signals sampled at 1MHz which interrupts the DSP at every 1 [Is. This research elaborates on designing a Quadrature Amplitude Modulator - demodulator (QAM) on the FPGA for the received signal from the ultrasound and edge detection on the DSP processor to detect the presence of edges/fractures on a test Sawbone plate. In this work, the LTP technology is applied to determine the location of the Sawbone plate edges based on the reflected signals to the receivers. This signal is then passed through a QAM to get the maxima (peaks) at the received signal to study the parameters in the DSP. This work successfully demonstrates the feasibility of modular programming approach across the two platforms. The dual time scale platform readily accommodates higher temporal resolution needed for the generation of Low Transient Pulses and the processing of real time baseband signals on the DSP for various test conditions

Cryptoraptor : high throughput reconfigurable cryptographic processor for symmetric key encryption and cryptographic hash functions

textIn cryptographic processor design, the selection of functional primitives and connection structures between these primitives are extremely crucial to maximize throughput and flexibility. Hence, detailed analysis on the specifications and requirements of existing crypto-systems plays a crucial role in cryptographic processor design. This thesis provides the most comprehensive literature review that we are aware of on the widest range of existing cryptographic algorithms, their specifications, requirements, and hardware structures. In the light of this analysis, it also describes a high performance, low power, and highly flexible cryptographic processor, Cryptoraptor, that is designed to support both today's and tomorrow's encryption standards. To the best of our knowledge, the proposed cryptographic processor supports the widest range of cryptographic algorithms compared to other solutions in the literature and is the only crypto-specific processor targeting the future standards as well. Unlike previous work, we aim for maximum throughput for all known encryption standards, and to support future standards as well. Our 1GHz design achieves a peak throughput of 128Gbps for AES-128 which is competitive with ASIC designs and has 25X and 160X higher throughput per area than CPU and GPU solutions, respectively.Electrical and Computer Engineerin

F1/10: An Open-Source Autonomous Cyber-Physical Platform

In 2005 DARPA labeled the realization of viable autonomous vehicles (AVs) a grand challenge; a short time later the idea became a moonshot that could change the automotive industry. Today, the question of safety stands between reality and solved. Given the right platform the CPS community is poised to offer unique insights. However, testing the limits of safety and performance on real vehicles is costly and hazardous. The use of such vehicles is also outside the reach of most researchers and students. In this paper, we present F1/10: an open-source, affordable, and high-performance 1/10 scale autonomous vehicle testbed. The F1/10 testbed carries a full suite of sensors, perception, planning, control, and networking software stacks that are similar to full scale solutions. We demonstrate key examples of the research enabled by the F1/10 testbed, and how the platform can be used to augment research and education in autonomous systems, making autonomy more accessible

THE VLIW-SUPERCISC COMPILER: EXPLOITINGPARALLELISM FROM C-BASED APPLICATIONS

A common approach to decreasing embedded application execution time is creating a homogeneous parallel processor architecture. The parallelism of any such architecture is limited to the number of instructions that can be scheduled in the same cycle. This number of instructions scheduled in a cycle, or instruction-level parallelism (ILP), is limited by the ability to extract parallelism from the application. Other techniques attempt to improve performance with hardware acceleration. Often, segments of highly computational extensive code are extracted and custom hardware is created to replace the software execution. This technique requires many resources and still does not address the segments of code outside of the computationally extensive kernel.To solve this problem, hardware acceleration for computationally intensive segments of code in addition to accelerating the entire application with very long instruction word, VLIW, techniques is proposed. (1) A compilation flow that targets a 4-wide VLIW processor architecture is presented. This system was used to investigate the available speed-up of VLIW architectures. The architecture was modified to combine the VLIW processor with the capability to execute application specific customized instructions. To create the custom instruction hardware, a control and data flow graph (CDFG) framework was created. The CDFG framework was created to provide a framework for compiler transformations and hardware generation. In order to remove control flow from segments of code selected for hardware generation, (2) the technique of hardware predication was developed. Hardware predication allows if-then and if-then-else control flow constructs to be transformed into strict data flow through the use of multiplexors. From the transformed CDFGs, (3) a VHDL generation pass was created that translates the compiler data structures into synthesizable VHDL. The resulting architecture contains the VLIW processor and tightly coupled application specific hardware. This architecture was analyzed for performance changes comparedto the initial VLIW architecture, and a traditional processor. Lastly, (4) the architecture was analyzed for power and energy savings. A post static timing pass was added to the compilation flow for the insertion of hardware to delay early switching of operations.By measuring only the execution of the hardware function and comparing the performance to the equivalent code executed in software, a performance multiplier of up to 322 times is seen when synthesized onto an Altera Stratix II ES2S180F1508C4 FPGA. The average performance increase seen was 63 times faster. For the entire application, the speedup reached nearly 30X and was on average 12X better than a single processor implementation. The power and energy required by the VLIW processor core and the hardware functions for the computational kernels after 160nm OKI standard cell ASIC synthesis show a maximum power savings of 417 times that of execution on the processor with an average of 133 times savings in power consumption. With the increased execution time and the savings in power the energy savings will see a multiplicative effect. The energy improvement is therefore several orders of magnitude for the hardware functions, the savings range from over 1,000X to approximately 60,000X

Concurrent Measurements of Inflow, Power Performance and Loads for a Grid-Synchronized Cross-Flow Turbine Operating in a Tidal Estuary

The adaptation of sustainable fluid energy conversion technologies, such as wind or tidalenergy, requires numerical modeling tools that are able to accurately predict device performance and loading in an effort to reduce the costs of turbines, deployment platforms and mooring structures. To validate models, data sets from turbines operating in real flow environments are required. Particularly for tidal energy, data sets of inflow (tidal current resource), power performance (electrical power and shaft speed), and thrust loading for any scale device are rare because the work to date has largely been funded by private developers and the data is not made publicly available. This “silos” the development of knowledge around operating devices to individual developers, which slows the pace of commercialization for the technology sector as a whole. The research project presented here utilized an existing tidal turbine, a modified New EnergyCorp EVG-025 vertical axis cross flow turbine (3.2m dia. X 1.7m tall), deployed at the UNH Tidal Energy Test Site at the Memorial Bridge in Portsmouth, NH. Significant improvements were made to the existing system, including the first grid synchronous operation, the development of a new data acquisition system (DAQ) and adding time synchronization across new and existing DAQ’s to allow for accurate performance and load characterization of the device. A significant data acquisition campaign was conducted during the fall of 2021, with over 750kWh hours of renewable tidal energy delivered to the NH grid during 29 days of turbine operation. Turbine power performance and thrust loading was characterized over a range of inflow operating conditions. Spectral analysis indicates the effects of turbulent structures on thrust loading and power output. The results further highlight the need for accurate instrument location and temporal resolution for accurate tidal resource characterization when siting new projects. This data set with all the concurrent measurements is sufficiently detailed for numerical model validation in real tidal flows. After significant quality control (QC) processing, the data set has been published in a public database, MHKR/PRIMRE. (Link: MHKDR-394

Forest Sign Maker

Executive Summary: The Inyo National Forest is arguably one of the most beautiful locations in California, containing natural masterpieces such as Mount Whitney and the Ancient Bristlecone Pine Forest. Despite its magnificence, the Inyo National Forest can be a treacherous region. The Friends of the Inyo take pride in being able to facilitate the viewing experience for all outdoorsmen by maintaining the mountain trails, which includes providing adequate trail signage. Unfortunately, there is a fundamental issue with the recent state of trail signage in the Inyo National Forest: the rate at which signs are being vandalized or naturally destroyed is greater than the rate at which signs can be produced. More specifically, the problem is that the current sign production process is completely manual; the process of routing the necessary letters and symbols consumes the majority of the production time, since it takes approximately two days to complete. Without adequate signage on the mountain trails, hikers and explorers are at a heightened risk for injury. We, the Cal Poly Forest Friends, have been commissioned by the Friends of the Inyo to resolve the issue of manufacturing trail signs. We plan on designing, building, and testing a prototype CNC machine for Paul McFarland, an employee of the Friends of the Inyo whom is responsible for replacing signs. This CNC machine can automatically produce a trail sign from a wooden blank so as to expedite the sign replacement process. By comparing different industry methods of etching letters into a wood substrate, researching all applicable signage guidelines for compliance, and optimizing the prototype design for the intended use cases, we have developed a low cost, high capacity CNC router that can be installed directly in Paul McFarland’s workshop. There has been much work done in the field of CNC machinery, so we believe it is feasible to design a functioning prototype that has been optimized for this purpose. The positional accuracy range of the machine will be broadened from the industry standard of ±0.0005 in to our requirement of ±0.063 inches. This optimized accuracy will allow for emphasis on increased workpiece capacity at a lower total cost. Additionally, by building the prototype CNC router as part of the Cal Poly Multidisciplinary Senior Project class, we will be able to adhere to the revised $3,500 budget. With a successful prototype in hand by June 2015, the sign production rate for the Friends of the Inyo will potentially increase tenfold, and provide the Friends of the Inyo with the ability to replace illegible trail signs within the Inyo National Forest