Towards Consistency Management for a Business-Driven Development of SOA

The usage of the Service Oriented Architecture (SOA) along with the Business Process Management has emerged as a valuable solution for the complex (business process driven) system engineering. With a Model Driven Engineering where the business process models drive the supporting service component architectures, less effort is gone into the Business/IT alignment during the initial development activities, and the IT developers can rapidly proceed with the SOA implementation. However, the difference between the design principles of the emerging domainspecific languages imposes serious challenges in the following re-design phases. Moreover, enabling evolutions on the business process models while keeping them synchronized with the underlying software architecture models is of high relevance to the key elements of any Business Driven Development (BDD). Given a business process update, this paper introduces an incremental model transformation approach that propagates this update to the related service component configurations. It, therefore, supports the change propagation among heterogenous domainspecific languages, e.g., the BPMN and the SCA. As a major contribution, our approach makes model transformation more tractable to reconfigure system architecture without disrupting its structural consistency. We propose a synchronizer that provides the BPMN-to-SCA model synchronization with the help of the conditional graph rewriting

FLICK: developing and running application-specific network services

Data centre networks are increasingly programmable, with application-specific network services proliferating, from custom load-balancers to middleboxes providing caching and aggregation. Developers must currently implement these services using traditional low-level APIs, which neither support natural operations on application data nor provide efficient performance isolation. We describe FLICK, a framework for the programming and execution of application-specific network services on multi-core CPUs. Developers write network services in the FLICK language, which offers high-level processing constructs and application-relevant data types. FLICK programs are translated automatically to efficient, parallel task graphs, implemented in C++ on top of a user-space TCP stack. Task graphs have bounded resource usage at runtime, which means that the graphs of multiple services can execute concurrently without interference using cooperative scheduling. We evaluate FLICK with several services (an HTTP load-balancer, a Memcached router and a Hadoop data aggregator), showing that it achieves good performance while reducing development effort

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Constant-time cost evaluation for behavioral partitioning

Given a system behavioral specification, partitioning can be used to distribute among chips the processes, procedures, and storage elements that comprise the specification. We introduce a technique for constant-time recomputation of pin, area, and execution-time estimates for a behavioral partitioning move. The technique permits fast, accurate estimations of a large number of partitionings, thus enabling better results than approaches which attain tractable computation time by using gross estimates or less thorough partitioning algorithms. The key to our technique is the isolation and extraction before partitioning of the basic design attributes needed for estimation, and the updating of this information in constant-time for each move. The estimation models are almost as detailed as those presented in previous estimation approaches not intended for constant-time update. The results we provide indicate the speed and practicality of our estimation approach in conjunction with sophisticated partitioning algorithms

Synthesis and Optimization of Reversible Circuits - A Survey

Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics. Recently, reversible circuits have attracted interest as components of quantum algorithms, as well as in photonic and nano-computing technologies where some switching devices offer no signal gain. Research in generating reversible logic distinguishes between circuit synthesis, post-synthesis optimization, and technology mapping. In this survey, we review algorithmic paradigms --- search-based, cycle-based, transformation-based, and BDD-based --- as well as specific algorithms for reversible synthesis, both exact and heuristic. We conclude the survey by outlining key open challenges in synthesis of reversible and quantum logic, as well as most common misconceptions.Comment: 34 pages, 15 figures, 2 table

Tomorrow's Metamaterials: Manipulation of Electromagnetic Waves in Space, Time and Spacetime

Metamaterials represent one of the most vibrant fields of modern science and technology. They are generally dispersive structures in the direct and reciprocal space and time domains. Upon this consideration, I overview here a number of metamaterial innovations developed by colleagues and myself in the holistic framework of space and time dispersion engineering. Moreover, I provide some thoughts regarding the future perspectives of the area

Architecture and noise analysis of continuous variable quantum gates using two-dimensional cluster states

Due to its unique scalability potential, continuous variable quantum optics is a promising platform for large scale quantum computing and quantum simulation. In particular, very large cluster states with a two-dimensional topology that are suitable for universal quantum computing and quantum simulation can be readily generated in a deterministic manner, and routes towards fault-tolerance via bosonic quantum error-correction are known. In this article we propose a complete measurement-based quantum computing architecture for the implementation of a universal set of gates on the recently generated two-dimensional cluster states [1,2]. We analyze the performance of the various quantum gates that are executed in these cluster states as well as in other two-dimensional cluster states (the bilayer-square lattice and quad-rail lattice cluster states [3,4]) by estimating and minimizing the associated stochastic noise addition as well as the resulting gate error probability. We compare the four different states and find that, although they all allow for universal computation, the quad-rail lattice cluster state performs better than the other three states which all exhibit similar performance

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas. © 2009 ACADEMY PUBLISHER