Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43016/1/10836_2004_Article_BF00136077.pd

A timing-driven pseudo-exhaustive testing of VLSI circuits

[[abstract]]The object of this paper is to reduce the delay penalty of bypass storage cell (bsc) insertion for pseudo-exhaustive testing. We first propose a tight delay lower bound algorithm which estimates the minimum circuit delay for each node after bsc insertion. By understanding how the lower bound algorithm loses optimality, we can propose a bsc insertion heuristic which tries to insert bscs so that the final delay is as close to the lower bound as possible. Our experiments show that the results of our heuristic are either optimal because they are the same as the delay lower bounds or they are very close to the optimal solutions.[[conferencetype]]國際[[conferencedate]]20000528~20000531[[booktype]]紙本[[conferencelocation]]Geneva, Switzerlan

Analyse de testabilité au niveau transfert de registres

Synthèse automatique et analyse de testabilité -- Les définitions de base -- Analyse de testabilité à haut niveau d'abstraction -- Analyse de testabilité et d'insertion de points de test au niveau transfert de registres -- Testability analysis and test-point insertion in RTL VHDL specifications for scan-based bist -- Implantation de l'algorithme et résultats expérimentaux

Embedding deterministic patterns in partial pseudo-exhaustive test

The topic of this thesis is related to testing of very large scale integration circuits. The thesis presents the idea of optimizing mixed-mode built-in self-test (BIST) scheme. Mixed-mode BIST consists of two phases. The first phase is pseudo-random testing or partial pseudo-exhaustive testing (P-PET). For the faults not detected by the first phase, deterministic test patterns are generated and applied in the second phase. Hence, the defect coverage of the first phase influences the number of patterns to be generated and stored. The advantages of P-PET in comparison with usual pseudo-random test are in obtaining higher fault coverage and reducing the number of deterministic patterns in the second phase of mixed-mode BIST. Test pattern generation for P-PET is achieved by selecting characteristic polynomials of multiple-polynomial linear feedback shift register (MP-LFSR). In this thesis, the mixed-mode BIST scheme with P-PET in the first phase is further improved in terms of the fault coverage of the first phase. This is achieved by optimization of polynomial selection of P-PET. In usual mixed-mode BIST, the set of undetected by the first phase faults is handled in the second phase by generating deterministic test patterns for them. The method in the thesis is based on consideration of these patterns during polynomial selection. In other words, we are embedding deterministic test patterns in P-PET. In order to solve the problem, the algorithm for the selection of characteristic polynomials covering the pre-generated patterns is developed. The advantages of the proposed approach in terms of the defect coverage and the number of faults left after the first phase are presented using contemporary industrial circuits. A comparison with usual pseudo-random testing is also performed. The results prove the benefits of P-PET with embedded test patterns in terms of the fault coverage, while maintaining comparable test length and time

Test set generation and optimisation using evolutionary algorithms and cubical calculus.

As the complexity of modern day integrated circuits rises, many of the challenges associated with digital testing rise exponentially. VLSI technology continues to advance at a rapid pace, in accordance with Moore's Law, posing evermore complex, NP-complete problems for the test community. The testing of ICs currently accounts for approximately a third of the overall design costs and according to the Semiconductor Industry Association, the per-transistor test cost will soon exceed the per-transistor production cost. Given the need to test ICs of ever-increasing complexity and to contain the cost of test, the problems of test pattern generation, testability analysis and test set minimisation continue to provide formidable challenges for the research community. This thesis presents original work in these three areas. Firstly, a new method is presented for generating test patterns for multiple output combinational circuits based on the Boolean difference method and cubical calculus. The Boolean difference method has been largely overlooked in automatic test pattern generation algorithms due to its cumbersome, algebraic nature. It is shown that cubical calculus provides an elegant and economical technique for solving Boolean difference equations. Formal mathematical techniques are presented involving the Boolean difference and cubical calculus providing, a test pattern generation method that dispenses with the need for costly circuit simulations. The methods provide the basis for test generation algorithms which are suitable for computer implementation. Secondly, some of the core test pattern generation computations outlined above also provide the basis of a new method for computing testability measures such as controllability and observability. This method is effectively a very economical spin-off of the test pattern generation process using Boolean differences and cubical calculus.The third and largest part of this thesis introduces a new test set minimization algorithm, GA-MITS, based on an evolutionary optimization algorithm. This novel approach applies a genetic algorithm to find minimal or near minimal test sets while maintaining a given fault coverage. The algorithm is designed as a postprocessor to minimise test sets that have been previously generated by an ATPG system and is thus considered a static approach to the test set minimisation problem. It is shown empirically that GA-MITS is remarkably successful in minimizing test sets generated for the ISCAS-85 benchmark circuits and hence potentially capable of reducing the production costs of realistic digital circuits

Modellierung und automatische Generierung von FPGA-basierten Testinstrumenten für den strukturellen Leiterplattentest

Neue Bauformen von Schaltkreisen wie BGAs führen zu sinkenden Möglichkeiten des optischen und mechanischen Testzugriffs und stellen Testsysteme vor Probleme bei der Testbarkeit von Verbindungen zwischen ICs auf Leiterplatten. Damit verbunden sind eine reduzierte Testabdeckung und steigende Kosten. Besonders für FPGAs fehlen geeignete Methoden, bei denen sich das Testsystem automatisch den Gegebenheiten der zu testenden Leiterplatte anpasst. Diese Dissertation beschäftigt sich mit dem Problem des FPGA-basierten Testens. Das vorgestellte Konzept nutzt ausschließlich vorhandene Ressourcen des FPGAs, um Testalgorithmen in dessen Logik zu implementieren und erhöht die Herstellungskosten der Leiterplatte nicht. Die Ressourcen des FPGAs stehen während der Testphase exklusiv für das Testen zur Verfügung. Ausgehend vom Stand der Technik nicht-invasiver elektrischer Verfahren für Leiterplattentests werden aktuelle Ansätze und Methoden miteinander verglichen. Aus deren Stärken und Schwächen wird eine detaillierte Zielstellung für diese Dissertation erarbeitet. Es wird eine Methode zur Generierung von Testinstrumenten für das FPGA-basierte Testen vorgestellt, die die Ausführung von Testalgorithmen in den FPGA verlagern und eine vergleichbare oder bessere Testabdeckung sowie Testgeschwindigkeit als etablierte Verfahren liefert, ohne dafür auf manuelle Eingriffe bei der Generierung angewiesen zu sein. Im Rahmen eines Lösungsansatzes wird neben der Testsystemarchitektur eine Modellierung für die an den Verbindungstests beteiligten Schaltkreise vorgestellt. Hierbei wird die Ausführung der Testalgorithmen im FPGA entweder in Software auf einem softcore-basierten Prozessor oder direkt in Hardware als diskrete Logik in einem sogenannten Co-Prozessor ermöglicht. Mit der Methode ist es möglich jeden Schaltkreis getrennt und unabhängig von der Art seiner späteren Implementierung und den konkreten Gegebenheiten des Prüflings zu modellieren. Die Generierung aller nötigen Bestandteile in Software und Hardware, wie auch deren Integration zu einem Testinstrument erfolgen dabei vollständig automatisch. Kern der Arbeit ist die Modellierung und Generierung für eingebettete Testinstrumente, die auf der Testsystemarchitektur basieren. Der Fokus wird dabei auf die zeitlich korrekte Ansteuerung der an den Verbindungstests beteiligten Schaltkreise gelegt, ohne dabei eine konkrete Implementierung vorzugeben. In Untersuchungen wird die Generierung von Testinstrumenten für verschiedene Schaltkreise betrachtet. Die Ergebnisse belegen die Leistungsfähigkeit der vorgestellten Methode zur automatischen Generierung von FPGA-basierten Testinstrumenten und zeigen eine signifikante Beschleunigung des FPGA-basierten Verbindungstests.New types of cases for integrated circuits like BGAs are leading to a decreased optical and mechanical test access. They are causing problems for test systems when testing connections between integrated circuits on printed circuit boards. This causes decreasing test coverage and increasing test costs. Especially for FPGAs some appropriate methods that automatically adapt the test system to the conditions of the printed circuit board are missing. This thesis is about the problems of FPGA-based testing. The presented concept solely uses available resources of the FPGA to transfer test algorithms from external test equipment into the programmable logic of the FPGA and therefore does not increase the production costs of the printed circuit board. The resources of the FPGA are exclusively used for testing during the test phase. Based on state-of-the-art non-invasive electrical methods for printed circuit boards with FPGAs current approaches are compared and analyzed. From the strengths and weaknesses of the considered methods a detailed description of the goals that should be achieved with this thesis is discussed. A method for the generation of so called test instruments for FPGA-based testing is presented. This method transfers the execution of test algorithms into the FPGA and has a similar or better test coverage as well as test speed compared to the well-established techniques without the need for any manually actions when generating such systems. Besides the chosen test system architecture the modeling of integrated circuits that are part of the connection test is presented. The test system architecture allows the execution of test algorithms either in software on a soft-core processor or directly in dedicated logic, so called co-processors. With this method it is possible to model each integrated circuit independent of each other and also independent of the implementation in software or hardware. The generation of all software and hardware parts of the test system is done fully automatically. Central element of this thesis is the modeling and generation of embedded test instruments, based on the presented test system architecture. The focus is on the timing-correct control routines of the integrated circuits that are part of the connection test. All parts of the test system should be modeled independent of each other and without knowledge about the use case. In experiments the generation of test instruments for different integrated circuits is carried out. These experiments prove the performance of the proposed methods for automatic generation of FPGA-based test instrument and show a significant speed-up for FPGA-based tests of printed circuit boards