366 research outputs found

    FPGA technology mapping optimizaion by rewiring algorithms.

    Get PDF
    Tang Wai Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 40-41).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.iiiChapter 1 --- Introduction --- p.1Chapter 2 --- Rewiring Algorithms --- p.3Chapter 2.1 --- REWIRE --- p.5Chapter 2.2 --- RAMFIRE --- p.7Chapter 2.3 --- GBAW --- p.8Chapter 3 --- FPGA Technology Mapping --- p.11Chapter 3.1 --- Problem Definition --- p.13Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16Chapter 3.2.1 --- FlowMap --- p.16Chapter 3.2.2 --- FlowSYN --- p.21Chapter 3.2.3 --- CutMap --- p.22Chapter 4 --- LUT Minimization by Rewiring --- p.24Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27Chapter 4.2 --- Experimental Result --- p.28Chapter 5 --- Conclusion --- p.38Bibliography --- p.4

    Improving rewiring scheme and its applications on various circuit design problems.

    Get PDF
    Lo Wing Hang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.Includes bibliographical references (leaves 60-61).Abstracts in English and Chinese.Abstract --- p.iChapter 1 --- Introduction --- p.1Chapter 2 --- Preliminaries --- p.5Chapter 2.1 --- Backgrounds and Definitions --- p.5Chapter 2.1.1 --- Boolean Network --- p.5Chapter 2.1.2 --- Transitive Fanin and Fanout Cone --- p.6Chapter 2.1.3 --- Controlling and Sensitizing Values --- p.6Chapter 2.1.4 --- Stuck-at Faults and Test Generation --- p.6Chapter 2.1.5 --- Mandatory Assignments --- p.8Chapter 2.2 --- Review of ATPG-based Rewiring --- p.9Chapter 3 --- Improved Single-Pass Rewiring Scheme Using Inconsistent Assignments --- p.14Chapter 3.1 --- Introduction --- p.14Chapter 3.2 --- Overview of FIRE --- p.15Chapter 3.3 --- Alternative Wire Identification Method --- p.17Chapter 3.3.1 --- Identifying Candidate Wires --- p.17Chapter 3.3.2 --- Redundancy Test on Candidate Wire --- p.18Chapter 3.4 --- Redundancy Identification Using Inconsistent Assignments --- p.21Chapter 3.5 --- Experimental Results --- p.26Chapter 3.6 --- Conclusions --- p.28Chapter 4 --- Improving Circuit Partitioning With Rewiring Techniques --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Implementation of Rewiring Schemes --- p.31Chapter 4.3 --- Coupling Partitioning Algorithm With Rewiring Techniques --- p.33Chapter 4.4 --- Experimental Results --- p.37Chapter 4.5 --- Conclusions --- p.43Chapter 5 --- Circuit Logic Level Reduction by Rewiring for FPGA Mapping --- p.45Chapter 5.1 --- Introduction --- p.45Chapter 5.2 --- Overview of the Technology Mapping Problem --- p.47Chapter 5.2.1 --- Problem Formulation --- p.47Chapter 5.2.2 --- FlowMap Algorithm Outline --- p.49Chapter 5.3 --- Logic Level Reduction by Rewiring Transformations --- p.51Chapter 5.4 --- Experimental Results --- p.54Chapter 5.5 --- Conclusions --- p.57Chapter 6 --- Conclusions and Future Works --- p.58Bibliography --- p.6

    Study of Single Event Transient Error Mitigation

    Get PDF
    Single Event Transient (SET) errors in ground-level electronic devices are a growing concern in the radiation hardening field. However, effective SET mitigation technologies which satisfy ground-level demands such as generic, flexible, efficient, and fast, are limited. The classic Triple Modular Redundancy (TMR) method is the most well-known and popular technique in space and nuclear environment. But it leads to more than 200% area and power overheads, which is too costly to implement in ground-level applications. Meanwhile, the coding technique is extensively utilized to inhibit upset errors in storage cells, but the irregularity of combinatorial logics limits its use in SET mitigation. Therefore, SET mitigation techniques suitable for ground-level applications need to be addressed. Aware of the demands for SET mitigation techniques in ground-level applications, this thesis proposes two novel approaches based on the redundant wire and approximate logic techniques. The Redundant Wire is a SET mitigation technique. By selectively adding redundant wire connections, the technique can prohibit targeted transient faults from propagating on the fly. This thesis proposes a set of signature-based evaluation equations to efficiently estimate the protecting effect provided by each redundant wire candidates. Based on the estimated results, a greedy algorithm is used to insert the best candidate repeatedly. Simulation results substantiate that the evaluation equations can achieve up to 98% accuracy on average. Regarding protecting effects, the technique can mask 18.4% of the faults with a 4.3% area, 4.4% power, and 5.4% delay overhead on average. Overall, the quality of protecting results obtained are 2.8 times better than the previous work. Additionally, the impact of synthesis constraints and signature length are discussed. Approximate Logic is a partial TMR technique offering a trade-off between fault coverage and area overheads. The approximate logic consists of an under-approximate logic and an over-approximate logic. The under-approximate logic is a subset of the original min-terms and the over-approximate logic is a subset of the original max-terms. This thesis proposes a new algorithm for generating the two approximate logics. Through the generating process, the algorithm considers the intrinsic failure probabilities of each gate and utilizes a confidence interval estimate equation to minimize required computations. The technique is applied to two fault models, Stuck-at and SET, and the separate results are compared and discussed. The results show that the technique can reduce the error 75% with an area penalty of 46% on some circuits. The delay overheads of this technique are always two additional layers of logic. The two proposed SET mitigation techniques are both applicable to generic combinatorial logics and with high flexibility. The simulation shows promising SET mitigation ability. The proposed mitigation techniques provide designers more choices in developing reliable combinatorial logic in ground-level applications

    Models for reducing power consumption in CPLD and FPGA devices

    Get PDF
    Usage of programmable logic devices PLD has increased in the latest years because of the ability to quickly implement complex types of electronic systems while reducing cost and time of synthesis. This technology enables dynamic reconfiguration of different applications according to specific requirements. Also, power consumption and its loss is becoming an increasingly important requirement in the design of systems for portable applications fed by batteries. Other factors to be taken into account in the consumption of power are elements that are used for manufacturing, packaging, and cooling systems. Power consumption must be taken into consideration especially for wireless applications where battery technologies provide power 20 W/h and voltage 1.2 volts. Despite improvements in battery technology, the development of methods for reducing power consumption plays a decisive role in portable applications. Therefore, modeling of power consumption has become a requirement with the highest impact in the performance of FPGA elements. Despite generated models of the different manufacturers of these elements, this article will appear comparisons of models based on experimental measurements performed on both CPLD and FPGA elements. Based on these models is selected to simulate a system that will be implemented in two elements and see how reduced power consumption, without affecting system performance. Experimental results show that FPGA elements have better performance and significantly reduce the power consumption

    LOT: Logic Optimization with Testability - new transformations for logic synthesis

    Get PDF
    A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

    Logic Synthesis for Established and Emerging Computing

    Get PDF
    Logic synthesis is an enabling technology to realize integrated computing systems, and it entails solving computationally intractable problems through a plurality of heuristic techniques. A recent push toward further formalization of synthesis problems has shown to be very useful toward both attempting to solve some logic problems exactly--which is computationally possible for instances of limited size today--as well as creating new and more powerful heuristics based on problem decomposition. Moreover, technological advances including nanodevices, optical computing, and quantum and quantum cellular computing require new and specific synthesis flows to assess feasibility and scalability. This review highlights recent progress in logic synthesis and optimization, describing models, data structures, and algorithms, with specific emphasis on both design quality and emerging technologies. Example applications and results of novel techniques to established and emerging technologies are reported

    Logic perturbation based circuit partitioning and optimum FPGA switch-box designs.

    Get PDF
    Cheung Chak Chung.Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.Includes bibliographical references (leaves 101-114).Abstracts in English and Chinese.Abstract --- p.iAcknowledgments --- p.iiiVita --- p.vTable of Contents --- p.viList of Figures --- p.xList of Tables --- p.xivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivation --- p.1Chapter 1.2 --- Aims and Contribution --- p.4Chapter 1.3 --- Thesis Overview --- p.5Chapter 2 --- VLSI Design Cycle --- p.6Chapter 2.1 --- Logic Synthesis --- p.7Chapter 2.1.1 --- Logic Minimization --- p.8Chapter 2.1.2 --- Technology Mapping --- p.8Chapter 2.1.3 --- Testability --- p.8Chapter 2.2 --- Physical Design Synthesis --- p.8Chapter 2.2.1 --- Partitioning --- p.9Chapter 2.2.2 --- Floorplanning & Placement --- p.10Chapter 2.2.3 --- Routing --- p.11Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12Chapter 2.2.5 --- Physical Design of FPGAs --- p.12Chapter 3 --- Alternative Wiring --- p.13Chapter 3.1 --- Introduction --- p.13Chapter 3.2 --- Notation and Definitions --- p.15Chapter 3.3 --- Application of Rewiring --- p.17Chapter 3.3.1 --- Logic Optimization --- p.17Chapter 3.3.2 --- Timing Optimization --- p.17Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18Chapter 3.4 --- Logic Optimization Analysis --- p.19Chapter 3.4.1 --- Global Flow Optimization --- p.19Chapter 3.4.2 --- OBDD Representation --- p.20Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23Chapter 3.5 --- Augmented GBAW --- p.26Chapter 3.6 --- Logic Optimization by using GBAW --- p.28Chapter 3.7 --- Conclusions --- p.31Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33Chapter 4.1 --- Introduction --- p.33Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53Chapter 4.4 --- Experimental Results --- p.56Chapter 4.5 --- Conclusions --- p.58Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62Chapter 5.1 --- Introduction --- p.62Chapter 5.2 --- Background and Definitions --- p.65Chapter 5.2.1 --- Routing Architectures --- p.65Chapter 5.2.2 --- Global Routing --- p.67Chapter 5.2.3 --- Detailed Routing --- p.67Chapter 5.3 --- FPGA Router Comparison --- p.69Chapter 5.3.1 --- CGE --- p.69Chapter 5.3.2 --- SEGA --- p.70Chapter 5.3.3 --- TRACER --- p.71Chapter 5.3.4 --- VPR --- p.72Chapter 5.4 --- Switch Box Design --- p.73Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73Chapter 5.4.2 --- Anti-symmetric switch box --- p.74Chapter 5.4.3 --- Universal Switch box --- p.74Chapter 5.4.4 --- Switch box Analysis --- p.75Chapter 5.5 --- Terminology --- p.77Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90Chapter 5.7 --- Experimental Results --- p.92Chapter 5.8 --- Conclusions --- p.95Chapter 6 --- Conclusions --- p.99Chapter 6.1 --- Thesis Summary --- p.99Chapter 6.2 --- Future work --- p.100Chapter 6.2.1 --- Alternative Wiring --- p.100Chapter 6.2.2 --- Partitioning Quality --- p.100Chapter 6.2.3 --- Routing Devices Studies --- p.100Bibliography --- p.101Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115Chapter B --- Proof of some 2-local patterns --- p.122Chapter C --- Illustrations of FM algorithm --- p.124Chapter D --- HUSB Structures --- p.127Chapter E --- Primitive minimal 4-way global routing Structures --- p.13

    CAD Automation Module Based On Cell Moving Algorithm For Incremental Placement Timing Optimization

    Get PDF
    Engineering Change Order (ECO) is a process to handle logic changes in circuit design. In deep sub-micron era, logic change in design happens inevitably. Design changes are required for numerous reasons. The reasons may be to fix design bugs, meeting design functionality change due to customer’s requirement or optimize design performance such as power consumption. An incremental placement that has the capability to handle design changes efficiently manages to save time and cost. This is why ECO remains one of the most influential steps in Very Large Scale Integration (VLSI) design. This thesis describes timing driven incremental placement that uses standard-cell move technique to improve timing of the layout design
    corecore