Development of an operational high refractive index resist for 193nm immersion lithography

Generation-three (Gen-3) immersion lithography offers the promise of enabling the 32nm half-pitch node. For Gen-3 lithography to be successful, however, there must be major breakthroughs in materials development: The hope of obtaining numerical aperture imaging 1.70 is dependent on a high index lens, fluid, and resist. Assuming that a fluid and a lens will be identified, this paper focuses on a possible path to a high index resist. Simulations have shown that the index of the resist should be 1.9 with any index higher than 1.9 leading to an increased process latitude. Creation of a high index resist from conventional chemistry has been shown to be unrealistic. The answer may be to introduce a high index, polarizable material into a resist that is inert relative to the polymer behavior, but will this too degrade the performance of the overall system? The specific approach is to add very high index (~2.9) nanoparticles to an existing resist system. These nanoparticles have a low absorbance; consequently the imaging of conventional 193nm resists does not degrade. Further, the nanoparticles are on the order of 3nm in diameter, thus minimizing any impact on line edge roughness (LER)

MAGIC: A European program to push the insertion of maskless lithography

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Skybridge: 3-D Integrated Circuit Technology Alternative to CMOS

Continuous scaling of CMOS has been the major catalyst in miniaturization of integrated circuits (ICs) and crucial for global socio-economic progress. However, scaling to sub-20nm technologies is proving to be challenging as MOSFETs are reaching their fundamental limits and interconnection bottleneck is dominating IC operational power and performance. Migrating to 3-D, as a way to advance scaling, has eluded us due to inherent customization and manufacturing requirements in CMOS that are incompatible with 3-D organization. Partial attempts with die-die and layer-layer stacking have their own limitations. We propose a 3-D IC fabric technology, Skybridge[TM], which offers paradigm shift in technology scaling as well as design. We co-architect Skybridge's core aspects, from device to circuit style, connectivity, thermal management, and manufacturing pathway in a 3-D fabric-centric manner, building on a uniform 3-D template. Our extensive bottom-up simulations, accounting for detailed material system structures, manufacturing process, device, and circuit parasitics, carried through for several designs including a designed microprocessor, reveal a 30-60x density, 3.5x performance per watt benefits, and 10X reduction in interconnect lengths vs. scaled 16-nm CMOS. Fabric-level heat extraction features are shown to successfully manage IC thermal profiles in 3-D. Skybridge can provide continuous scaling of integrated circuits beyond CMOS in the 21st century.Comment: 53 Page

Alternative Lithographic Methods for Variable Aspect Ratio Vias

The foundation of semiconductor industry has historically been driven by scaling. Device size reduction is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Aggressive reductions in memory cell size have resulted in systems with diminishing area between parallel bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently difficult to resolve because of their relatively small area, a product of their two domain critical dimension image. To accommodate these trends there has been a shift toward the implementation of elliptical contact features. This empowers designers to maximize the use of free space between bit/word lines and gate stacks while preserving contact area; effectively reducing the minor via axis dimension while maintaining a patternable threshold in increasingly dense circuitry. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect ratio vias for implementation in electronic design systems. This work separately investigates two unique, non-traditional lithographic techniques in the integration of an optical vortex mask as well as a polymer assembly system as means to augment ellipticity while facilitating contact feature scaling. This document affords a fundamental overview of imaging theory, details previous literature as to the technological trends enabling the resolving of contact features and demonstrates simulated & empirical evidence that the described methods have great potential to extend the resolution of variable aspect ratio vias using lithographic technologies

E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System

Electron beam lithography (EBL) is a promising maskless solution for the technology beyond 14nm logic node. To overcome its throughput limitation, recently the traditional EBL system is extended into MCC system. %to further improve the throughput. In this paper, we present E-BLOW, a tool to solve the overlapping aware stencil planning (OSP) problems in MCC system. E-BLOW is integrated with several novel speedup techniques, i.e., successive relaxation, dynamic programming and KD-Tree based clustering, to achieve a good performance in terms of runtime and solution quality. Experimental results show that, compared with previous works, E-BLOW demonstrates better performance for both conventional EBL system and MCC system

Image-based EUVL Aberration Metrology

A significant factor in the degradation of nanolithographic image fidelity is optical wavefront aberration. As resolution of nanolithography systems increases, effects of wavefront aberrations on aerial image become more influential. The tolerance of such aberrations is governed by the requirements of features that are being imaged, often requiring lenses that can be corrected with a high degree of accuracy and precision. Resolution of lithographic systems is driven by scaling wavelength down and numerical aperture (NA) up. However, aberrations are also affected from the changes in wavelength and NA. Reduction in wavelength or increase in NA result in greater impact of aberrations, where the latter shows a quadratic dependence. Current demands in semiconductor manufacturing are constantly pushing lithographic systems to operate at the diffraction limit; hence, prompting a need to reduce all degrading effects on image properties to achieve maximum performance. Therefore, the need for highly accurate in-situ aberration measurement and correction is paramount. In this work, an approach has been developed in which several targets including phase wheel, phase disk, phase edges, and binary structures are used to generate optical images to detect and monitor aberrations in extreme ultraviolet (EUV) lithographic systems. The benefit of using printed patterns as opposed to other techniques is that the lithography system is tested under standard operating conditions. Mathematical models in conjunction with iterative lithographic simulations are used to determine pupil phase wavefront errors and describe them as combinations of Zernike polynomials

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Threat Analysis, Countermeaures and Design Strategies for Secure Computation in Nanometer CMOS Regime

Advancements in CMOS technologies have led to an era of Internet Of Things (IOT), where the devices have the ability to communicate with each other apart from their computational power. As more and more sensitive data is processed by embedded devices, the trend towards lightweight and efficient cryptographic primitives has gained significant momentum. Achieving a perfect security in silicon is extremely difficult, as the traditional cryptographic implementations are vulnerable to various active and passive attacks. There is also a threat in the form of hardware Trojans inserted into the supply chain by the untrusted third-party manufacturers for economic incentives. Apart from the threats in various forms, some of the embedded security applications such as random number generators (RNGs) suffer from the impacts of process variations and noise in nanometer CMOS. Despite their disadvantages, the random and unique nature of process variations can be exploited for generating unique identifiers and can be of tremendous use in embedded security. In this dissertation, we explore techniques for precise fault-injection in cryptographic hardware based on voltage/temperature manipulation and hardware Trojan insertion. We demonstrate the effectiveness of these techniques by mounting fault attacks on state-of-the-art ciphers. Physically Unclonable Functions (PUFs) are novel cryptographic primitives for extracting secret keys from complex manufacturing variations in integrated circuits (ICs). We explore the vulnerabilities of some of the popular strong PUF architectures to modeling attacks using Machine Learning (ML) algorithms. The attacks use silicon data from a test chip manufactured in IBM 32nm silicon-on-insulator (SOI) technology. Attack results demonstrate that the majority of strong PUF architectures can be predicted to very high accuracies using limited training data. We also explore the techniques to exploit unreliable data from strong PUF architectures and effectively use them to improve the prediction accuracies of modeling attacks. Motivated by the vulnerabilities of existing PUF architectures, we present a novel modeling attack resistant PUF architecture based on non-linear computing elements. Post-silicon validation results are used to demonstrate the effectiveness of the non-linear PUF architecture against modeling and fault-injection attacks. Apart from the techniques to improve the security of PUF circuits, we also present novel solutions to improve the performance of PUF circuits from the perspectives of IC fabrication and system/protocol design. Finally, we present a statistical benchmark suite to evaluate PUFs in conceptualization phase and also to enable fine-grained security assessments for varying PUF parameters. Data compressibility analyses for validating the statistical benchmark suite are also presented