Through Silicon Via Field-Effect Transistor with Hafnia-based Ferroelectrics and the Doping of Silicon by Gallium Implantation Utilizing a Focused Ion Beam System

3-dimensional integration has become a standard to further increase the transistor density and to enhance the integrated functionality in microchips. Integrated circuits are stacked on top of each other and copper-filled through-silicon VIAs (TSVs) are the industry-accepted choice for their vertical electrical connection. The aim of this work is to functionalize the TSVs by implementing vertical field-effect transistors inside the via holes. The front and back sides of 200 ... 300 µm thin silicon wafers were doped to create the source/drain regions of n- and p-FETs. The TSVFETs showed very stable saturation currents and on/off current ratios of about 10^6 (n-TSVFET) and 10^3 (p-TSVFET) for a gate voltage magnitude of 4V. The use of hafnium zirconium oxide on a thin SiO_2 interface layer as gate dielectric material in a p-TSVFET, enabled the implementation of a charge trapping memory inside the TSVs, showing a memory window of about 1V. This allows the non-volatile storage of the transistor on/off state. In addition, the demonstration of the use of gallium as the source/drain dopant in planar p-FET test structures (ion implanted from a focused ion beam tool) paves the way for maskless doping and for a process flow with a low thermal budget. It was shown, that ion implanted gallium can be activated and annealed at relatively low temperatures of 500 °C ... 700 °C.:Abstract / Kurzzusammenfassung Danksagung Index I List of Figures III List of Tables X List of Symbols XI List of Abbreviations XV 1 Introduction 1 2 Fundamentals 5 2.1 Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) 5 2.1.1 Historical Development - Technological Advancements 7 2.1.2 Field-Effect Transistors in Semiconductor Memories 10 2.2 3D Integration and the Use of TSVs (Through Silicon VIAs) 16 2.3 Doping of Silicon 19 2.3.1 Doping by Thermal Diffusion 20 2.3.2 Doping by Ion Implantation 22 3 Electrical Characterization 24 3.1 Resistivity Measurements 24 3.1.1 Resistance Determination by Four-Point Probes Measurement 24 3.1.2 Contact Resistivity 27 3.1.3 Doping Concentration 32 3.2 C-V Measurements 35 3.2.1 Fundamentals of MIS C-V Measurements 35 3.2.2 Interpretation of C-V Measurements 37 3.3 Transistor Measurements 41 3.3.1 Output Characteristics (I_D-V_D) 41 3.3.2 Transfer Characteristics (I_D-V_G) 42 4 TSV Transistor 45 4.1 Idea and Motivation 45 4.2 Design and Layout of the TSV Transistor 47 4.2.1 Design of the TSV Transistor Structures 47 4.2.2 Test Structures for Planar FETs 48 5 Variations in the Integration Scheme of the TSV Transistor 51 5.1 Doping by Diffusion from Thin Films 51 5.1.1 Determination of Doping Profiles 52 5.1.2 n- and p- TSVFETs Doped Manufactures by the Use of the Diffusion Technique 59 5.2 Ferroelectric Hafnium-Zirconium-Oxide (HZO) in the Gate Stack 81 5.2.1 Planar ferroelectric p-MOSFETs Doped by Thermal Diffusion 82 5.2.2 p-TSVFETs with Hafnium-Zirconium-Oxide Metal Gate 90 5.3 Doping by Ion Implantation of Gallium with a Focused Ion Beam (FIB) Tool 96 5.3.1 Ga doped Si Diodes 97 5.3.2 Planar p-MOSFETs Doped by Ga Implantation 108 5.3.3 Proposal for a parallel integration of Cu TSVs and p-TSVFETs 117 6 Summary and Outlook 120 Bibliography XVIII A Appendix XXXVI A.1 Resistivity and Dopant Density XXXVI A.2 Mask set for the TSVFET XXXVII A.3 Mask Design of the Planar Test Structures XXXVIII Curriculum Vitae XXXIX List of Scientific Publications XL

Fault and Defect Tolerant Computer Architectures: Reliable Computing With Unreliable Devices

This research addresses design of a reliable computer from unreliable device technologies. A system architecture is developed for a fault and defect tolerant (FDT) computer. Trade-offs between different techniques are studied and yield and hardware cost models are developed. Fault and defect tolerant designs are created for the processor and the cache memory. Simulation results for the content-addressable memory (CAM)-based cache show 90% yield with device failure probabilities of 3 x 10(-6), three orders of magnitude better than non fault tolerant caches of the same size. The entire processor achieves 70% yield with device failure probabilities exceeding 10(-6). The required hardware redundancy is approximately 15 times that of a non-fault tolerant design. While larger than current FT designs, this architecture allows the use of devices much more likely to fail than silicon CMOS. As part of model development, an improved model is derived for NAND Multiplexing. The model is the first accurate model for small and medium amounts of redundancy. Previous models are extended to account for dependence between the inputs and produce more accurate results

Ionizing Radiation Effects on Graphene Based Field Effects Transistors

Graphene, first isolated in 2004 by Andre Geim and Konstantin Novoselov, is an atomically thin two-dimensional layer of hexagonal carbon that has been extensively studied due to its unique electronic, mechanical, thermal and optical properties. Its vast potential has led to the development of a wide variety of novel devices such as, transistors, solar cells, batteries and sensors that offer significant advantages over the conventional microelectronic ones. Although graphene-based devices show very promising performance characteristics, limited has been done in order to evaluate how these devices operate in a radiation harsh environment. Undesirable phenomena such as total dose effects, single event upsets, displacement damage and soft errors that silicon-based devices are prone to, can have a detrimental impact on performance and reliability. Similarly, the significant effects of irradiation on carbon nanotubes indicate the potential for related radiation induced defects in carbon-based materials, such as graphene. In this work, we fabricate graphene field effect transistors (GFETs) and systematically study the various effects of ionizing radiation on the material and device level. Graphene grown by chemical vapor deposition (CVD) along with standard lithographic and shadow masking techniques, was used for the transistor fabrication. GFETs were subjected to different radiation sources, such as, beta particles (electron radiation), gamma (photons) and ions (alpha, protons and Fe particles) under various radiation doses and energies. The effects on graphene’s crystal structure, transport properties and doping profile were examined by using a variety of characterization tools and techniques. We demonstrate not only the mechanisms of ionized charge build up in the substrate and displacement damage effects on GFET performance, but also that atmospheric adsorbents from the surrounding environment can have a significant impact on the radiation hardness of graphene. We developed different transistor structures that mitigate these effects and performed computer simulations to enhance even further our understanding of radiation damage. Our results show that devices using a passivation layer and a shielded gate structure were less prone to irradiation effects when compared to the standard back-gate GFETs, offering less performance degradation and enhanced stability over prolonged irradiation periods. This is an important step towards the development of radiation hard graphene-based devices, enabling operation in space, military, or other radiation sensitive environments

Control and characterization of a spin-orbit-driven singlet-triplet qubit in silicon

Les spins dans les semi-conducteurs sont d’excellents candidats pour l’implémentation d’un ordinateur quantique universel puisqu’ils sont compacts, peuvent être opérés à des températures relativement élevées, ont le potentiel d’atteindre des temps de cohérence très longs, et peuvent être combinés avec d’autres technologies quantiques pour former des systèmes hybrides. En particulier, les dispositifs fabriqués en silicium isotopiquement enrichi offrent des fidélités accrues et ont un processus de fabrication compatible avec les techniques utilisées dans les fonderies CMOS. Cette thèse étudie un qubit singulet-triplet confiné dans une boîte quantique double en silicium isotopiquement enrichi. Dans la première partie, cette thèse montre comment caractériser et ajuster la double boîte pour atteindre le régime de contrôle désiré. Une méthode numérique est développée pour trianguler la position des boîtes quantiques et des donneurs implantés dans le substrat. Un nouveau modèle permettant de prédire les taux tunnel en fonction des voltages de grille est également proposé, puis vérifié expérimentalement. Dans la deuxième partie, cette thèse montre comment implémenter le contrôle résolu en temps d’un qubit singulettriplet entraîné par l’interaction spin-orbite. Deux méthodes différentes permettant d’implémenter des rotations arbitraire sur un qubit sont démontrées : la méthode pulsée (DC) et la méthode résonante (AC). Il est montré que le régime où le qubit est fortement entraîné peut être atteint à l’aide de ces portes résonantes. Finalement, la tomographie d’ensemble de portes (gate set tomography) est utilisée pour comparer ces deux types de portes logiques. Les résultats semblent indiquer que les portes résonantes sont de plus haute fidélité que les portes pulsées, et cela malgré le fait qu’elles soient plus lentes et qu’elles aient un facteur de qualité plus petit que ces dernières. Ces travaux sont les premiers à utiliser cette méthode tomographique pour caractériser des rotations autour de deux axes non-orthogonaux.Abstract : Spins in semiconductors are attractive candidates for a universal quantum computer because they are compact, can be operated at relatively high temperature, have potentially long coherence times, and can be combined with other quantum technologies to form hybrid systems. Devices made using isotopically-enriched silicon offer the additional advantages of increased coherence time due to the relative absence of nuclear spins, and compatibility with existing CMOS foundry fabrication techniques. This work studies a singlet-triplet qubit formed in an enriched silicon metal-oxide-semiconductor double quantum dot device. The first part of this thesis presents techniques that are useful for characterizing the double-dot device and tuning it to the few electron regime. A capacitance-based numerical method is developed to triangulate the position of quantum dots and implanted donor atoms. Additionally, a new model that predicts dot-lead tunnel rates for varying gate voltages is proposed and its validity is demonstrated over a wide range of values. The second part of this thesis shows how to perform time domain control on a spin-orbit-driven singlet-triplet qubit. Two different methods for performing arbitrary single-qubit rotations are demonstrated: fast DC-controlled pulses, and slower resonantly-driven AC pulses. Evidence of the resonantly-driven pulses being pushed to the strongly-driven regime is shown. The final part of this thesis uses gate set tomography to compare the fidelity of these two types of single-qubit operations. Preliminary results seem to indicate that the resonantly-driven rotations have a higher fidelity than the DC-controlled operations despite the fact that the former are slower and have a smaller quality factor than the latter. This work constitutes the first time that gate set tomography is used to characterize a non-orthogonal set of gates

Inorganic micro/nanostructures-based high-performance flexible electronics for electronic skin application

Electronics in the future will be printed on diverse substrates, benefiting several emerging applications such as electronic skin (e-skin) for robotics/prosthetics, flexible displays, flexible/conformable biosensors, large area electronics, and implantable devices. For such applications, electronics based on inorganic micro/nanostructures (IMNSs) from high mobility materials such as single crystal silicon and compound semiconductors in the form of ultrathin chips, membranes, nanoribbons (NRs), nanowires (NWs) etc., offer promising high-performance solutions compared to conventional organic materials. This thesis presents an investigation of the various forms of IMNSs for high-performance electronics. Active components (from Silicon) and sensor components (from indium tin oxide (ITO), vanadium pentaoxide (V2O5), and zinc oxide (ZnO)) were realised based on the IMNS for application in artificial tactile skin for prosthetics/robotics. Inspired by human tactile sensing, a capacitive-piezoelectric tandem architecture was realised with indium tin oxide (ITO) on a flexible polymer sheet for achieving static (upto 0.25 kPa-1 sensitivity) and dynamic (2.28 kPa-1 sensitivity) tactile sensing. These passive tactile sensors were interfaced in extended gate mode with flexible high-performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated through a scalable process. The developed process enabled wafer scale transfer of ultrathin chips (UTCs) of silicon with various devices (ultrathin chip resistive samples, metal oxide semiconductor (MOS) capacitors and n‐channel MOSFETs) on flexible substrates up to 4″ diameter. The devices were capable of bending upto 1.437 mm radius of curvature and exhibited surface mobility above 330 cm2/V-s, on-to-off current ratios above 4.32 decades, and a subthreshold slope above 0.98 V/decade, under various bending conditions. While UTCs are useful for realizing high-density high-performance micro-electronics on small areas, high-performance electronics on large area flexible substrates along with low-cost fabrication techniques are also important for realizing e-skin. In this regard, two other IMNS forms are investigated in this thesis, namely, NWs and NRs. The controlled selective source/drain doping needed to obtain transistors from such structure remains a bottleneck during post transfer printing. An attractive solution to address this challenge based on junctionless FETs (JLFETs), is investigated in this thesis via technology computer-aided design (TCAD) simulation and practical fabrication. The TCAD optimization implies a current of 3.36 mA for a 15 μm channel length, 40 μm channel width with an on-to-off ratio of 4.02x 107. Similar to the NRs, NWs are also suitable for realizing high performance e-skin. NWs of various sizes, distribution and length have been fabricated using various nano-patterning methods followed by metal assisted chemical etching (MACE). Synthesis of Si NWs of diameter as low as 10 nm and of aspect ratio more than 200:1 was achieved. Apart from Si NWs, V2O5 and ZnO NWs were also explored for sensor applications. Two approaches were investigated for printing NWs on flexible substrates namely (i) contact printing and (ii) large-area dielectrophoresis (DEP) assisted transfer printing. Both approaches were used to realize electronic layers with high NW density. The former approach resulted in 7 NWs/μm for bottom-up ZnO and 3 NWs/μm for top-down Si NWs while the latter approach resulted in 7 NWs/μm with simultaneous assembly on 30x30 electrode patterns in a 3 cm x 3 cm area. The contact-printing system was used to fabricate ZnO and Si NW-based ultraviolet (UV) photodetectors (PDs) with a Wheatstone bridge (WB) configuration. The assembled V2O5 NWs were used to realize temperature sensors with sensitivity of 0.03% /K. The sensor arrays are suitable for tactile e-skin application. While the above focuses on realizing conventional sensing and addressing elements for e-skin, processing of a large amount of data from e-skin has remained a challenge, especially in the case of large area skin. A Neural NW Field Effect Transistors (υ-NWFETs) based hardware-implementable neural network (HNN) approach for tactile data processing in e-skin is presented in the final part of this thesis. The concept is evaluated by interfacing with a fabricated kirigami-inspired e-skin. Apart from e-skin for prosthetics and robotics, the presented research will also be useful for obtaining high performance flexible circuits needed in many futuristic flexible electronics applications such as smart surgical tools, biosensors, implantable electronics/electroceuticals and flexible mobile phones

The Fifth National Technology Transfer Conference and Exposition

No abstract availabl

A New electronic image array: The Active pixel charge injection device

This is a Ph.D. thesis dissertation in which a new type of image sensor is investigated as possible successor to the charge coupled device (CCD) for scientific applications. As a result of the work described in this dissertation, the active pixel charge injection device (AP-CID) has been developed. This device retains most of the positive features of both the charge injection device (CJD) imager (random readout, non destructive readout, antiblooming, increased UV sensitivity, radiation tolerance, low power consumption, low manufacturing price) and the CCD imager (low noise, high dynamic range). The device lacks most of the drawbacks of the aforementioned devices. A functional array architecture was created. Based on this architecture several devices were fabricated. One of the arrays was fully measured, characterized and suggestions for improvement were formulated. Most of the characterizationalysis work described in this dissertation was centered on the following issues: temporal noise, linearity and FPN. The measured noise performance of the new device is excellent and comparable to the noise performance of the scientific CCD. The newly developed sensor is necessary for scientific imaging applications in space based operation. However due to its qualities, this device could be used in a much wider range of applications including commercial digital cameras, spectroscopy, biological, nuclear and other scientific applications

Single-crystal germanium growth on amorphous silicon

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2011.Cataloged from PDF version of thesis.Includes bibliographical references (p. 130-136).The integration of photonics with electronics has emerged as a leading platform for microprocessor technology and the continuation of Moore's Law. As electronic device dimensions shrink, electronic signals encounter crippling delays and heating issues such that signal transduction across large on-chip distances becomes increasingly more difficult. However, these issues may be mitigated by the use of photonic interconnects combined with electronic devices in electronic-photonic integrated circuits (EPICs). The electronics in proposed EPIC designs perform the logic operations and short-distance signal transmission, while photonic devices serve to transmit signals over longer lengths. However, the photonic devices are large compared to electronic devices, and thus the two types of devices would ideally exist on separate levels of the microprocessor stack in order to maximize the amount of silicon substrate available for electronic device fabrication. A CMOS-compatible back-end process for the fabrication of photonic devices is necessary to realize such a three-dimensional EPIC. Back-end processing is limited in thermal budget and does not present a single-crystal substrate for epitaxial growth, however, so high-quality crystal fabrication methods currently used for photonic device fabrication are not possible in back-end processing. This thesis presents a method for the fabrication of high-quality germanium single crystals using CMOS-compatible back-end processing. Initial work on the ultra-high vacuum chemical vapor deposition of polycrystalline germanium on amorphous silicon is presented. The deposition can be successfully performed by using a pre-growth hydrofluoric acid dip and by limiting the thickness of the amorphous silicon layer to less than 120 nm. Films deposited at temperatures of 350° C, 450° C, and 550° C show (110) texture, though the texture is most prevalent in growths at 450° C. Poly-Ge grown at 4500 C is successfully doped n-type in situ, and the grain size of as-grown material is enhanced by lateral growth over a barrier. Structures are fabricated for the growth of Ge confined in one dimension. The growths show faceting across large areas, in contrast to as-deposited poly-Ge, corresponding to enhanced grain sizes. Growth confinement is shown to reduce the defect density as the poly-Ge grows. When coalesced into a continuous film, the material grown from 1 D confinement exhibits a lower carrier density and lower trap density than as-deposited poly-Ge, indicating improved material quality. We measure an increased grain size from as-deposited poly-Ge to Ge grown from ID confinement. Single-crystal germanium is grown at 450° C from confinement in two dimensions. Such growths exhibit faceting across the entire crystal as well as the presence of E3 boundaries ({111} twins), with many growths showing no other boundaries. These twins mediate the growth of the crystal, as they serve as the points for heterogeneous surface nucleation of adatom clusters. The twins can form after the crystal nucleates and are strongly preferred in order to obtain appreciable crystal growth rates. We model the growths from the confining channels in order to find the optimum channel geometry for large, uniform, single-crystal growths that consistently emerge from the channel. The growths from 2D confinement show lower trap density than those from 1 D confinement, indicating a further enhancement of the crystal quality due to the increased confinement. This method of single-crystal growth from an amorphous substrate is extensible to any materials system in which selective non-epitaxial deposition is possible.by Kevin A. McComber.Ph.D