Mixed-Signal Neural Network Implementation with Programmable Neuron

This thesis introduces implementation of mixed-signal building blocks of an artificial neural network; namely the neuron and the synaptic multiplier. This thesis, also, investigates the nonlinear dynamic behavior of a single artificial neuron and presents a Distributed Arithmetic (DA)-based Finite Impulse Response (FIR) filter. All the introduced structures are designed and custom laid out

Recent Results on Some Word Oriented Stream Ciphers: SNOW 1.0, SNOW 2.0 and SNOW 3G

In this chapter, we have studied three word-oriented stream ciphers SNOW 1.0, SNOW 2.0 and SNOW 3G in a detailed way. The detailed description includes the working principles of each cipher, security vulnerabilities and implementation issues. It also helps us to study the challenges in each cipher. As SNOW 3G is used as a confidentiality and integrity component in 3G, 4G and 5G communications, the after study of this article may instigate the reader to find the fixes from different cryptanalysis and also find a new suitable design in Mobile telephony security

Novel Predistortion System for 4G/5G Small-Cell and Wideband Transmitters

To meet the growing demand for mobile data, various technologies are being introduced to wireless networks to increase system capacity. On one hand, large number of small-cell base stations are adopted to serve the reduced cell size; on the other hand, millimeter wave (mm-wave) systems with large antenna arrays that transmit ultra-wideband signals are expected in fifth generation (5G) networks. Power amplifiers (PAs), responsible for boosting the radio frequency (RF) signal power, are the most critical components in base station transmitters, and dominate the overall efficiency and linearity of the system. The design challenges to balance the contradictory requirements of efficiency and linearity of the PAs are usually addressed by linearization techniques, particularly the digital predistortion (DPD) system. However, existing DPD solutions face increasing difficulties keeping up with new developments in base station technologies. When considering sub-6 GHz small-cell base station transmitters, analog and RF predistortion techniques have recently received renewed attention due to their inherent low power nature. Their achievable linearization capacity is significantly limited, however, largely by their implementation complexity in realizing the needed predistortion models in analog circuitry. On the other hand, despite significant developments in DPD models for wideband signals, the implementations of such DPD models in practical hardware have received relatively little attention. Yet the conventional implementation of a DPD engine is limited by the maximum clock frequency of the digital circuitry employed and cannot be scaled to satisfy the growing bandwidth of transmitted signals for 5G networks. Furthermore, both analog and digital solutions require a transmitter-observation-receiver (TOR) to capture the PA outputs, necessitates the use of analog-to-digital converters (ADCs) whose complexity and power consumption increase with signal bandwidth. Such trend is not scalable for future base stations, and new innovations in feedback and training methods are required. This thesis presents a number of contributions to address the above identified challenges. To reduce the power overhead of the linearization system, a digitally-assisted analog-RF predistortion (DA-ARFPD) system that uses a novel predistortion model is introduced. The proposed finite-impulse-response assisted envelope memory polynomial (FIR-EMP) model allows for a reduction of hardware implementation complexity while maintaining good linearization capacity and low power overhead. A two-step small-signal-assisted parameter identification (SSAPI) algorithm is devised to estimate the parameters of the two main blocks of the FIR-EMP model, such that the training can be completed efficiently. A DA-ARFPD test bench has been built, which incorporates major RF components, to assess the validity of the proposed FIR-EMP scheme and the SSAPI algorithm. Measurement results show that the proposed FIR-EMP model with SSAPI algorithm can successfully linearize multiple PAs driven with various wideband and carrier-aggregated signals of up to 80~MHz modulation bandwidths for sub-6 GHz systems. Next, a hardware-efficient real-time DPD system with scalable linearization bandwidth for ultra-wideband 5G mm-wave transmitters is proposed. It uses a novel parallel-processing DPD engine architecture to process multiple samples per clock cycle, overcomes the linearization bandwidth limit imposed by the maximum clock rate of digital circuits used in conventional DPD implementation. Potentially unlimited linearization bandwidth could be achieved by using the proposed system with current digital circuit technologies. The linearization performance and bandwidth scalability of the proposed system is demonstrated experimentally using a silicon-based Doherty (DPA) with 400 MHz wideband signal operating at 28 GHz, and over-the-air measurements using a 64-element beamforming array with 800 MHz wideband signal, also at 28 GHz. The proposed DPD system achieves over 2.4 GHz linearization bandwidth using only a 300 MHz core clock for the digital circuits. Finally, to reduce the power consumption and cost of the TOR, a new approach to train the predistorter using under-sampled feedback signal is presented. Using aliased samples of the PA's output captured at either baseband or intermedia frequency (IF), the proposed algorithm is able to compute the coefficients of the predistortion engine to linearize the PA using a direct learning architecture. Experimentally, both the baseband and IF schemes achieve linearization performance comparable to a full-rate system. Implemented together with a parallel-processing based DPD engine on a field-programmable gate array (FPGA) based system-on-chip (SOC), the proposed feedback and training solution achieves over 2.4~GHz linearization bandwidth using an ADC operating at a clock rate of 200 MHz. Its performance is demonstrated experimentally by linearizing a silicon DPA with 200 MHz and 400 MHz signals in conductive measurements, and a 64-element beamforming array with 400 MHz and 800 MHz signals in over-the-air testing

Real-Time FPGA-Based Testbed for Evaluating Digital Predistortion in Fully Digital MIMO Transmitters

As one of the key enabling technologies of 5G networks, massive multiple-input, multiple-output (MIMO) transmitters use many transmit chains to ensure a very high data rate and acceptable signal quality. Realizing Massive MIMO not only includes increasing antenna count but also requires proportionally more power amplifiers (PAs). Digital predistortion (DPD) is a well-established signal processing method that mitigates the non-linearities of a PA when operated near saturation. Design tradeoffs must be carefully considered to reduce the system's overall power requirements given the high PA count in MIMO systems. This implies DPD power consumption for each transmission chain must be minimized. Apart from this, larger transmission bandwidths in next-generation networks require high hardware clock rates on the order of a few gigahertz. Current hardware can satisfy clock rates of up to hundreds of megahertz. Thus, there is a need for parallelized signal processing methods to meet bandwidth requirements. This thesis investigates and addresses some challenges for deploying massive MIMO systems by designing and building a reconfigurable digital signal processing (DSP) testbed that allows for the implementation and validation of real-time DSP algorithms including DPD, for fully digital massive MIMO transceivers. This testbed allows transmission of up to 16 fully digital transmission chains at sub-6 GHz frequencies and supports up to 120 MHz of modulation bandwidths. Finally, a low-complexity and parallelized piecewise-linear (PWL) dual-input dual-output (DISO) DPD solution is proposed for linearizing MIMO transmitters. This DPD solution is realized with a commercially available field-programmable-gate-array (FPGA)

Linearization using Digital Predistortion of a High-Speed, Pulsed, Radio Frequency Power Amplifier for VHF Radar Depth-Sounder Systems

Depth-sounding radar systems provide the scientific data that are useful in modeling polar ice sheets and predicting sea-level rise. These radars are typically deployed on crewed aircraft; however, crewed missions over polar regions are difficult and dangerous. Thus, CReSIS is developing uninhabited aerial vehicles (UAVs) from which fine-resolution measurements can be made over vast areas. These fine-resolution measurements require highly linear power amplifiers (PAs) to create low range side-lobe levels. However, highly linear PAs are typically less efficient and require large and bulky heat sinks for heat dissipation, which increases the payload weight and decreases flight time. Furthermore, the linear FM chirp signal used for these radar systems creates Fresnel ripples and side-lobes will be generated when there are deviations from the ideal rectangular spectrum amplitude even with efficient windowing techniques, such as a Tukey window. Therefore, a 100 W, high-speed, pulsed, VHF power amplifier was developed and linearized using memoryless digital predistortion (DP) to obtain high linearity and high efficiency. The DP linearization decreased near-range side-lobe levels 11 dB from -46 dBc to -57 dBc, with a maximum reduction in the far-range side-lobe levels of 17 dB over the Tukey (transmit) and Blackmann2 (receive) windowing alone. The high-speed switching circuit reduced current consumption to 117 mA (or 3.28 W at +28 V) for a 10-us pulse at 1-kHz PRF

A high-accuracy optical linear algebra processor for finite element applications

Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced