Definability by constant-depth polynomial-size circuits

A function of boolean arguments is symmetric if its value depends solely on the number of 1's among its arguments. In the first part of this paper we partially characterize those symmetric functions that can be computed by constant-depth polynomial-size sequences of boolean circuits, and discuss the complete characterization. (We treat both uniform and non-uniform sequences of circuits.) Our results imply that these circuits can compute functions that are not definable in first-order logic. In the second part of the paper we generalize from circuits computing symmetric functions to circuits recognizing first-order structures. By imposing fairly natural restrictions we develop a circuit model with precisely the power of first-order logic: a class of structures is first-order definable if and only if it can be recognized by a constant-depth polynomial-time sequence of such circuits.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/26084/1/0000160.pd

Applications of Derandomization Theory in Coding

Randomized techniques play a fundamental role in theoretical computer science and discrete mathematics, in particular for the design of efficient algorithms and construction of combinatorial objects. The basic goal in derandomization theory is to eliminate or reduce the need for randomness in such randomized constructions. In this thesis, we explore some applications of the fundamental notions in derandomization theory to problems outside the core of theoretical computer science, and in particular, certain problems related to coding theory. First, we consider the wiretap channel problem which involves a communication system in which an intruder can eavesdrop a limited portion of the transmissions, and construct efficient and information-theoretically optimal communication protocols for this model. Then we consider the combinatorial group testing problem. In this classical problem, one aims to determine a set of defective items within a large population by asking a number of queries, where each query reveals whether a defective item is present within a specified group of items. We use randomness condensers to explicitly construct optimal, or nearly optimal, group testing schemes for a setting where the query outcomes can be highly unreliable, as well as the threshold model where a query returns positive if the number of defectives pass a certain threshold. Finally, we design ensembles of error-correcting codes that achieve the information-theoretic capacity of a large class of communication channels, and then use the obtained ensembles for construction of explicit capacity achieving codes. [This is a shortened version of the actual abstract in the thesis.]Comment: EPFL Phd Thesi

Preimages for SHA-1

This research explores the problem of finding a preimage — an input that, when passed through a particular function, will result in a pre-specified output — for the compression function of the SHA-1 cryptographic hash. This problem is much more difficult than the problem of finding a collision for a hash function, and preimage attacks for very few popular hash functions are known. The research begins by introducing the field and giving an overview of the existing work in the area. A thorough analysis of the compression function is made, resulting in alternative formulations for both parts of the function, and both statistical and theoretical tools to determine the difficulty of the SHA-1 preimage problem. Different representations (And- Inverter Graph, Binary Decision Diagram, Conjunctive Normal Form, Constraint Satisfaction form, and Disjunctive Normal Form) and associated tools to manipulate and/or analyse these representations are then applied and explored, and results are collected and interpreted. In conclusion, the SHA-1 preimage problem remains unsolved and insoluble for the foreseeable future. The primary issue is one of efficient representation; despite a promising theoretical difficulty, both the diffusion characteristics and the depth of the tree stand in the way of efficient search. Despite this, the research served to confirm and quantify the difficulty of the problem both theoretically, using Schaefer's Theorem, and practically, in the context of different representations

Measurements, Models, Systems and Design

531 s.

SAT-based preimage attacks on SHA-1

Hash functions are important cryptographic primitives which map arbitrarily long messages to fixed-length message digests in such a way that: (1) it is easy to compute the message digest given a message, while (2) inverting the hashing process (e.g. finding a message that maps to a specific message digest) is hard. One attack against a hash function is an algorithm that nevertheless manages to invert the hashing process. Hash functions are used in e.g. authentication, digital signatures, and key exchange. A popular hash function used in many practical application scenarios is the Secure Hash Algorithm (SHA-1). In this thesis we investigate the current state of the art in carrying out preimage attacks against SHA-1 using SAT solvers, and we attempt to find out if there is any room for improvement in either the encoding or the solving processes. We run a series of experiments using SAT solvers on encodings of reduced-difficulty versions of SHA-1. Each experiment tests one aspect of the encoding or solving process, such as e.g. determining whether there exists an optimal restart interval or determining which branching heuristic leads to the best average solving time. An important part of our work is to use statistically sound methods, i.e. hypothesis tests which take sample size and variation into account. Our most important result is a new encoding of 32-bit modular addition which significantly reduces the time it takes the SAT solver to find a solution compared to previously known encodings. Other results include the fact that reducing the absolute size of the search space by fixing bits of the message up to a certain point actually results in an instance that is harder for the SAT solver to solve. We have also identified some slight improvements to the parameters used by the heuristics of the solver MiniSat; for example, contrary to assertions made in the literature, we find that using longer restart intervals improves the running time of the solver

Multiple-Input Common-Gate FGUVMOS Transistor and Its Application in Multiple-Valued Logic Circuits

The demand for reduced area and power consumption have usually been met with improvements in processing techniques, allowing for increased integration and a reduction in the power supply voltage. Some technology improvements have also occurred, such as strained silicon and silicon-on-insulator. But some design techniques also feature a significant reduction in area and power consumption, such the asynchronous design approach. Reducing the amount of interconnects is another approach, for which multiple-valued logic might be an ideal candidate. This thesis explores the multiple-input common-gate FGUVMOS transistor and the design of multiple-valued logic circuits using this transistor. We examine in detail a UV-programming technique for initializing the floating-gate. There is no need for any extra programming circuitry with this programming method, since it utilizes the supply rail of the nMOS transistor to place a charge on the floating-gate. An important benefit of the floating-gate initialization is a matching of the pMOS and nMOS transistor at a predetermined current level. We also look closer at some of the layout issues concerning FGUVMOS circuits. We also explore a new area of application for the FGUVMOS transistor, namely multiple-valued logic. The main design parameter of the FGUVMOS transistor--the capacitive division ratios of the coupling capacitors to the floating-gate--is well suited for designing voltage-mode multiple-valued logic circuits. Several multiple-valued logic circuits are examined in detail and several design issues are addressed. Measurements on a fabricated chip are supplied, as well as simulations of the various circuits. And the voltage output functions for the presented circuits are also developed

Waveform narrowing : a constraint-based framework for timing analysis

Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2