Metodologia Per la Caratterizzazione di amplificatori a basso rumore per UMTS

In questo lavoro si presenta una metodologia di progettazione elettronica a livello di sistema, affrontando il problema della caratterizzazione dello spazio di progetto dell' amplificatore a basso rumore costituente il primo stadio di un front end a conversione diretta per UMTS realizzato in tecnologia CMOS con lunghezza di canale .18u. La metodologia è sviluppata al fine di valutare in modo quantititativo le specifiche ottime di sistema per il front-end stesso e si basa sul concetto di Piattaforma Analogica, che prevede la costruzione di un modello di prestazioni per il blocco analogico basato su campionamento statistico di indici di prestazioni del blocco stesso, misurati tramite simulazione di dimensionamenti dei componenti attivi e passivi soddisfacenti un set di equazioni specifico della topologia circuitale. Gli indici di prestazioni vengono successivamente ulizzati per parametrizzare modelli comportamentali utilizzati nelle fasi di ottimizzazione a livello di sistema. Modelli comportamentali atti a rappresentare i sistemi RF sono stati pertanto studiati per ottimizzare la scelta delle metriche di prestazioni. L'ottimizzazione dei set di equazioni atti a selezionare le configurazione di interesse per il campionamento ha al tempo stesso richiesto l'approfondimento dei modelli di dispositivi attivi validi in tutte le regioni di funzionamento, e lo studio dettagliato della progettazione degli amplificatori a basso rumore basati su degenerazione induttiva. Inoltre, il problema della modellizzazione a livello di sistema degli effetti della comunicazione tra LNA e Mixer è stato affrontato proponendo e analizzando diverse soluzioni. Il lavoro ha permesso di condurre un'ottimizzazione del front-end UMTS, giungendo a specifiche ottime a livello di sistema per l'amplificatore stesso

HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS

Tohoku University堀口 進課

Automated Netlist Generation for 3D Electrothermal and Electromagnetic Field Problems

We present a method for the automatic generation of netlists describing general three-dimensional electrothermal and electromagnetic field problems. Using a pair of structured orthogonal grids as spatial discretisation, a one-to-one correspondence between grid objects and circuit elements is obtained by employing the finite integration technique. The resulting circuit can then be solved with any standard available circuit simulator, alleviating the need for the implementation of a custom time integrator. Additionally, the approach straightforwardly allows for field-circuit coupling simulations by appropriately stamping the circuit description of lumped devices. As the computational domain in wave propagation problems must be finite, stamps representing absorbing boundary conditions are developed as well. Representative numerical examples are used to validate the approach. The results obtained by circuit simulation on the generated netlists are compared with appropriate reference solutions.Comment: This is a pre-print of an article published in the Journal of Computational Electronics. The final authenticated version is available online at: https://dx.doi.org/10.1007/s10825-019-01368-6. All numerical results can be reproduced by the Matlab code openly available at https://github.com/tc88/ANTHE

The effect of heterogeneity on decorrelation mechanisms in spiking neural networks: a neuromorphic-hardware study

High-level brain function such as memory, classification or reasoning can be realized by means of recurrent networks of simplified model neurons. Analog neuromorphic hardware constitutes a fast and energy efficient substrate for the implementation of such neural computing architectures in technical applications and neuroscientific research. The functional performance of neural networks is often critically dependent on the level of correlations in the neural activity. In finite networks, correlations are typically inevitable due to shared presynaptic input. Recent theoretical studies have shown that inhibitory feedback, abundant in biological neural networks, can actively suppress these shared-input correlations and thereby enable neurons to fire nearly independently. For networks of spiking neurons, the decorrelating effect of inhibitory feedback has so far been explicitly demonstrated only for homogeneous networks of neurons with linear sub-threshold dynamics. Theory, however, suggests that the effect is a general phenomenon, present in any system with sufficient inhibitory feedback, irrespective of the details of the network structure or the neuronal and synaptic properties. Here, we investigate the effect of network heterogeneity on correlations in sparse, random networks of inhibitory neurons with non-linear, conductance-based synapses. Emulations of these networks on the analog neuromorphic hardware system Spikey allow us to test the efficiency of decorrelation by inhibitory feedback in the presence of hardware-specific heterogeneities. The configurability of the hardware substrate enables us to modulate the extent of heterogeneity in a systematic manner. We selectively study the effects of shared input and recurrent connections on correlations in membrane potentials and spike trains. Our results confirm ...Comment: 20 pages, 10 figures, supplement

Transient electrothermal simulation of power semiconductor devices

In this paper, a new thermal model based on the Fourier series solution of heat conduction equation has been introduced in detail. 1-D and 2-D Fourier series thermal models have been programmed in MATLAB/Simulink. Compared with the traditional finite-difference thermal model and equivalent RC thermal network, the new thermal model can provide high simulation speed with high accuracy, which has been proved to be more favorable in dynamic thermal characterization on power semiconductor switches. The complete electrothermal simulation models of insulated gate bipolar transistor (IGBT) and power diodes under inductive load switching condition have been successfully implemented in MATLAB/Simulink. The experimental results on IGBT and power diodes with clamped inductive load switching tests have verified the new electrothermal simulation model. The advantage of Fourier series thermal model over widely used equivalent RC thermal network in dynamic thermal characterization has also been validated by the measured junction temperature

Lifetime Estimation of IGBTs in a Grid-connected STATCOM

Lifetime estimation of power semiconductor devices, and IGBT devices in particular, used in the power electronics integrated with power systems has gained technical importance in recent times with increased scope of distributed generation, renewable energy systems and FACTS. Since most of the common failures (wire bond and solder fatigue) are caused by thermo-mechanical stresses, the methodology of lifetime estimation starts with temperature estimation, cycle counting based on rainflow algorithm, and finally degradation calculation based on linear accumulation model. Different number of RC cells for each packaging layer in the module for the thermal model, including the influence of encapsulant is proposed for temperature estimation of IGBTs in power modules. A modified rainflow algorithm with faster execution time and time dependent temperature calculation is introduced for cycle counting. Finally, the lifetime of the IGBT is estimated during STATCOM operation using real-time load profiles for power factor variation. For a power factor variation data for a building, the lifetime is estimated to be about 3 years. Similarly, a month long arc furnace load data is considered to compare the equivalent temperature based calculation to conventional tests. 4% more degradation is observed in the equivalent temperature based calculation than compared with conventional rainflow algorithm. A simulation study on the operation parameter dependence on the stresses in a wire is considered to estimate lifetime from Finite Element Analysis (FEA) in COMSOL. Power cycling tests are conducted on two different modules (600 V, 50 A H-bridge module and a 1200 V, 150 A phase leg module) to validate the lifetime model for four months. The low power module was tested without any protection circuits and hence failed catastrophically. Wire melt-off or fusing failure was dominantly observed, following by dielectric based short circuit failure. The high power module was tested with protection circuits to prevent catastrophic damage for a maximum of 4 months. A maximum of 20% degradation in static characteristics, with decreased on state resistance was observed in the modules. The degradation is attributed to increased junction temperature as the thermal resistance increases owing to solder fatigue