94 research outputs found

    Gate-level timing analysis and waveform evaluation

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    Static timing analysis (STA) is an integral part of modern VLSI chip design. Table lookup based methods are widely used in current industry due to its fast runtime and mature algorithms. Conventional STA algorithms based on table-lookup methods are developed under many assumptions in timing analysis; however, most of those assumptions, such as that input signals and output signals can be accurately modeled as ramp waveforms, are no longer satisfactory to meet the increasing demand of accuracy for new technologies. In this dissertation, we discuss several crucial issues that conventional STA has not taken into consideration, and propose new methods to handle these issues and show that new methods produce accurate results. In logic circuits, gates may have multiple inputs and signals can arrive at these inputs at different times and with different waveforms. Different arrival times and waveforms of signals can cause very different responses. However, multiple-input transition effects are totally overlooked by current STA tools. Using a conventional single-input transition model when multiple-input transition happens can cause significant estimation errors in timing analysis. Previous works on this issue focus on developing a complicated gate model to simulate the behavior of logic gates. These methods have high computational cost and have to make significant changes to the prevailing STA tools, and are thus not feasible in practice. This dissertation proposes a simplified gate model, uses transistor connection structures to capture the behavior of multiple-input transitions and requires no change to the current STA tools. Another issue with table lookup based methods is that the load of each gate in technology libraries is modeled as a single lumped capacitor. But in the real circuit, the Abstract 2 gate connects to its subsequent gates via metal wires. As the feature size of integrated circuit scales down, the interconnection cannot be seen as a simple capacitor since the resistive shielding effect will largely affect the equivalent capacitance seen from the gate. As the interconnection has numerous structures, tabulating the timing data for various interconnection structures is not feasible. In this dissertation, by using the concept of equivalent admittance, we reduce an arbitrary interconnection structure into an equivalent π-model RC circuit. Many previous works have mapped the π-model to an effective capacitor, which makes the table lookup based methods useful again. However, a capacitor cannot be equivalent to a π-model circuit, and will thus result in significant inaccuracy in waveform evaluation. In order to obtain an accurate waveform at gate output, a piecewise waveform evaluation method is proposed in this dissertation. Each part of the piecewise waveform is evaluated according to the gate characteristic and load structures. Another contribution of this dissertation research is a proposed equivalent waveform search method. The signal waveforms can be very complicated in the real circuits because of noises, race hazards, etc. The conventional STA only uses one attribute (i.e., transition time) to describe the waveform shape which can cause significant estimation errors. Our approach is to develop heuristic search functions to find equivalent ramps to approximate input waveforms. Here the transition time of a final ramp can be completely different from that of the original waveform, but we can get higher accuracy on output arrival time and transition time. All of the methods mentioned in this dissertation require no changes to the prevailing STA tools, and have been verified across different process technologies

    Energy Reduction Techniques to Increase Battery Life for Electronic Sensor Nodes

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    Preserving battery life in duty-cycled sensor nodes requires minimizing energy use in the active region. Lowering the power supply of CMOS gates down into sub-threshold mode is a good way to decrease energy. In this work, a unique technique to control the current in CMOS gates to reliably operate them in sub-threshold mode is described. Compared to the current state-of-theart for running digital gates in the sub-threshold regime, this work is often superior in its lack of complexity and in reduced variance in delay caused by process variations. In addition to presenting the design considerations, a demonstration of a complete digital design flow is given using the custom gates. An AES128 encryption/decryption engine is designed using the aforementioned digital flow in a commercial 180nm process. The resulting design has a ratio of maximum to minimum frequency variation over corners of only 50% with a 0.3V power supply where the same ratio with standard CMOS gates biased under the same supply voltage is 5600%. In addition, the custom gates are used to design a Wallace tree multiplier in an SOI 45nm process that is fully functional with an optimum energy power supply level of 0.34V with a typical operating frequency of 8 MHz having a variation over corners of 80%. For a proof of concept memory chip designed in this work, the architecture uses a logiccompatible CMOS process particularly suitable for embedded applications. The differential pair construct causes the read and refresh power to be independent of any process parameter including the within-die threshold voltage. The current stop feature keeps the read voltage transition low to further minimize read power. The bit cell operates in both single bit BASE2 and multi-bit BASE4 modes. An expression for the read signal was verified with bit cell simulations. These simulations also compare the performance impact of threshold voltage variance in the architecture with a standard gain cell. A DRAM bit cell array was fabricated in the XFab 180nm CMOS process. Measured waveforms closely match theoretical results obtained from a system simulation. The silicon retention time was measured at room temperature and is greater than 150 ms in BASE2 mode and greater than 75 ms in BASE4 mode. 180nm, 25C analysis predicts 0.8uW/Mbit refresh power at 630 MHz, the lowest in the literature. Further: the memory bit cell architecture presented here has a refresh power delay product several times lower than any other published architecture. The current controlled memory architecture in this work improves or overcomes the drawbacks of the 1T1C and gain cell memory architectures. A current controlled memory design was fabricated as a 131K bit array in an 180nm process to provide silicon proof. The bit cell configuration with shared read and write bit cells gives effectively two memory banks. The grouping of rows together into common source domains allows only two opamps to control the current in all the bit cells across the whole chip. The sense amplifiers have a globally controlled switching threshold point and keep their static power in the nano-amp range. The bit cells can operate either in BASE2 or BASE4 mode and the read bit line transitions are reduced with a current stop construct. Parts were received from the foundry in an 84-pin PLCC and were tested at a number of locations on the die. They proved to be fully functional in BASE4. The silicon retention time was measured at room temperature and was greater than four seconds

    Modeling and Simulation of Advanced Nano-Scale Very Large Scale Integration Circuits

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    With VLSI(very large scale integration) technology shrinking and frequency increasing, the minimum feature size is smaller than sub-wavelength lithography wavelength, and the manufacturing cost is significantly increasing in order to achieve a good yield. Consequently design companies need to further lower power consumption. All these factors bring new challenges; simulation and modeling need to handle more design constraints, and need to work with modern manufacturing processes. In this dissertation, algorithms and new methodology are presented for these problems: (1) fast and accurate capacitance extraction, (2) capacitance extraction considering lithography effect, (3) BEOL(back end of line) impact on SRAM(static random access memory) performance and yield, and (4) new physical synthesis optimization flow is used to shed area and reduce the power consumption. Interconnect parasitic extraction plays an important role in simulation, verification, optimization. A fast and accurate parasitic extraction algorithm is always important for a current design automation tool. In this dissertation, we propose a new algorithm named HybCap to efficiently handle multiple planar, conformal or embedded dielectric media. From experimental results, the new method is significantly faster than the previous one, 77X speedup, and has a 99% memory savings compared with FastCap and 2X speedup, and has an 80% memory savings compared with PHiCap for complex dielectric media. In order to consider lithography effect in the existing LPE(Layout Parasitic Extraction) flow, a modified LPE flow and fast algorithms for interconnect parasitic extraction are proposed in this dissertation. Our methodology is efficient, compatible with the existing design flow and has high accuracy. With the new enhanced parasitic extraction flow, simulation of BEOL effect on SRAM performance becomes possible. A SRAM simulation model with internal cell interconnect RC parasitics is proposed in order to study the BEOL lithography impact. The impact of BEOL variations on memory designs are systematically evaluated in this dissertation. The results show the power estimation with our SRAM model is more accurate. Finally, a new optimization flow to shed area blow in the design synthesis flow is proposed, which is one level beyond simulation and modeling to directly optimize design, but is also built upon accurate simulations and modeling. Two simple, yet efficient, buffering and gate sizing techniques are presented. On 20 industrial designs in 45nm and 65nm, our new work achieves 12.5% logic area growth reduction, 5.8% total area reduction, 10% wirelength reduction and 770 ps worst slack improvement on average

    A p-cell approach to integer gate sizing

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    Standard-Cell-library-based design ow is widely followed in the Application Specific Integrated Circuit(ASIC) industry. Most of the realistic cell libraries are geometrically spaced introducing significant sparseness in the library. This is because uniformly spaced gate sizes would result in a large number of gate sizes and maintaining the huge volume of data for this number of gate sizes is difficult. This thesis aims to propose a practical approach to implement integer gate sizes. A parameterized cell (p-cell) approach to the generation of layouts of standard gates is presented. The use of constant delay model for gate delay estimation is proposed which eliminates the need for maintaining huge volumes of delay tables in the standard cell library. This approach has tremendous potential since it greatly simplifies the standard-cell-based design methodology and can give significant power and area savings.Power and area savings of up to 28% are possible using this approach
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