Least-Squares Approximation and Polyphase Decomposition for Pipelining Recursive filters

Current techniques used in pipelining recursive filters require high hardware complexity. These techniques attempt to preserve the exact frequency response of the original circuit while seeking to construct a pipelined architecture. We present a technique that relaxes the need to preserve the exact frequency response and instead considers a least-squares formulation in conjunction with the pipelined architecture. The benefit of this design is that it reduces the complexity of the pipelined circuit immensely, while enabling a simple pipelined architecture based on a polyphase decomposition of the original filter

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

Design and Implementation of Complexity Reduced Digital Signal Processors for Low Power Biomedical Applications

Wearable health monitoring systems can provide remote care with supervised, inde-pendent living which are capable of signal sensing, acquisition, local processing and transmission. A generic biopotential signal (such as Electrocardiogram (ECG), and Electroencephalogram (EEG)) processing platform consists of four main functional components. The signals acquired by the electrodes are amplified and preconditioned by the (1) Analog-Front-End (AFE) which are then digitized via the (2) Analog-to-Digital Converter (ADC) for further processing. The local digital signal processing is usually handled by a custom designed (3) Digital Signal Processor (DSP) which is responsible for either anyone or combination of signal processing algorithms such as noise detection, noise/artefact removal, feature extraction, classification and compres-sion. The digitally processed data is then transmitted via the (4) transmitter which is renown as the most power hungry block in the complete platform. All the afore-mentioned components of the wearable systems are required to be designed and fitted into an integrated system where the area and the power requirements are stringent. Therefore, hardware complexity and power dissipation of each functional component are crucial aspects while designing and implementing a wearable monitoring platform. The work undertaken focuses on reducing the hardware complexity of a biosignal DSP and presents low hardware complexity solutions that can be employed in the aforemen-tioned wearable platforms. A typical state-of-the-art system utilizes Sigma Delta (Σ∆) ADCs incorporating a Σ∆ modulator and a decimation filter whereas the state-of-the-art decimation filters employ linear phase Finite-Impulse-Response (FIR) filters with high orders that in-crease the hardware complexity [1–5]. In this thesis, the novel use of minimum phase Infinite-Impulse-Response (IIR) decimators is proposed where the hardware complexity is massively reduced compared to the conventional FIR decimators. In addition, the non-linear phase effects of these filters are also investigated since phase non-linearity may distort the time domain representation of the signal being filtered which is un-desirable effect for biopotential signals especially when the fiducial characteristics carry diagnostic importance. In the case of ECG monitoring systems the effect of the IIR filter phase non-linearity is minimal which does not affect the diagnostic accuracy of the signals. The work undertaken also proposes two methods for reducing the hardware complexity of the popular biosignal processing tool, Discrete Wavelet Transform (DWT). General purpose multipliers are known to be hardware and power hungry in terms of the number of addition operations or their underlying building blocks like full adders or half adders required. Higher number of adders leads to an increase in the power consumption which is directly proportional to the clock frequency, supply voltage, switching activity and the resources utilized. A typical Field-Programmable-Gate-Array’s (FPGA) resources are Look-up Tables (LUTs) whereas a custom Digital Signal Processor’s (DSP) are gate-level cells of standard cell libraries that are used to build adders [6]. One of the proposed methods is the replacement of the hardware and power hungry general pur-pose multipliers and the coefficient memories with reconfigurable multiplier blocks that are composed of simple shift-add networks and multiplexers. This method substantially reduces the resource utilization as well as the power consumption of the system. The second proposed method is the design and implementation of the DWT filter banks using IIR filters which employ less number of arithmetic operations compared to the state-of-the-art FIR wavelets. This reduces the hardware complexity of the analysis filter bank of the DWT and can be employed in applications where the reconstruction is not required. However, the synthesis filter bank for the IIR wavelet transform has a higher computational complexity compared to the conventional FIR wavelet synthesis filter banks since re-indexing of the filtered data sequence is required that can only be achieved via the use of extra registers. Therefore, this led to the proposal of a novel design which replaces the complex IIR based synthesis filter banks with FIR fil-ters which are the approximations of the associated IIR filters. Finally, a comparative study is presented where the hybrid IIR/FIR and FIR/FIR wavelet filter banks are de-ployed in a typical noise reduction scenario using the wavelet thresholding techniques. It is concluded that the proposed hybrid IIR/FIR wavelet filter banks provide better denoising performance, reduced computational complexity and power consumption in comparison to their IIR/IIR and FIR/FIR counterparts

Efficient algorithms for arbitrary sample rate conversion with application to wave field synthesis

Arbitrary sample rate conversion (ASRC) is used in many fields of digital signal processing to alter the sampling rate of discrete-time signals by arbitrary, potentially time-varying ratios. This thesis investigates efficient algorithms for ASRC and proposes several improvements. First, closed-form descriptions for the modified Farrow structure and Lagrange interpolators are derived that are directly applicable to algorithm design and analysis. Second, efficient implementation structures for ASRC algorithms are investigated. Third, this thesis considers coefficient design methods that are optimal for a selectable error norm and optional design constraints. Finally, the performance of different algorithms is compared for several performance metrics. This enables the selection of ASRC algorithms that meet the requirements of an application with minimal complexity. Wave field synthesis (WFS), a high-quality spatial sound reproduction technique, is the main application considered in this work. For WFS, sophisticated ASRC algorithms improve the quality of moving sound sources. However, the improvements proposed in this thesis are not limited to WFS, but applicable to general-purpose ASRC problems.Verfahren zur unbeschränkten Abtastratenwandlung (arbitrary sample rate conversion,ASRC) ermöglichen die Änderung der Abtastrate zeitdiskreter Signale um beliebige, zeitvarianteVerhältnisse. ASRC wird in vielen Anwendungen digitaler Signalverarbeitung eingesetzt.In dieser Arbeit wird die Verwendung von ASRC-Verfahren in der Wellenfeldsynthese(WFS), einem Verfahren zur hochqualitativen, räumlich korrekten Audio-Wiedergabe, untersucht.Durch ASRC-Algorithmen kann die Wiedergabequalität bewegter Schallquellenin WFS deutlich verbessert werden. Durch die hohe Zahl der in einem WFS-Wiedergabesystembenötigten simultanen ASRC-Operationen ist eine direkte Anwendung hochwertigerAlgorithmen jedoch meist nicht möglich.Zur Lösung dieses Problems werden verschiedene Beiträge vorgestellt. Die Komplexitätder WFS-Signalverarbeitung wird durch eine geeignete Partitionierung der ASRC-Algorithmensignifikant reduziert, welche eine effiziente Wiederverwendung von Zwischenergebnissenermöglicht. Dies erlaubt den Einsatz hochqualitativer Algorithmen zur Abtastratenwandlungmit einer Komplexität, die mit der Anwendung einfacher konventioneller ASRCAlgorithmenvergleichbar ist. Dieses Partitionierungsschema stellt jedoch auch zusätzlicheAnforderungen an ASRC-Algorithmen und erfordert Abwägungen zwischen Performance-Maßen wie der algorithmischen Komplexität, Speicherbedarf oder -bandbreite.Zur Verbesserung von Algorithmen und Implementierungsstrukturen für ASRC werdenverschiedene Maßnahmen vorgeschlagen. Zum Einen werden geschlossene, analytischeBeschreibungen für den kontinuierlichen Frequenzgang verschiedener Klassen von ASRCStruktureneingeführt. Insbesondere für Lagrange-Interpolatoren, die modifizierte Farrow-Struktur sowie Kombinationen aus Überabtastung und zeitkontinuierlichen Resampling-Funktionen werden kompakte Darstellungen hergeleitet, die sowohl Aufschluss über dasVerhalten dieser Filter geben als auch eine direkte Verwendung in Design-Methoden ermöglichen.Einen zweiten Schwerpunkt bildet das Koeffizientendesign für diese Strukturen, insbesonderezum optimalen Entwurf bezüglich einer gewählten Fehlernorm und optionaler Entwurfsbedingungenund -restriktionen. Im Gegensatz zu bisherigen Ansätzen werden solcheoptimalen Entwurfsmethoden auch für mehrstufige ASRC-Strukturen, welche ganzzahligeÜberabtastung mit zeitkontinuierlichen Resampling-Funktionen verbinden, vorgestellt.Für diese Klasse von Strukturen wird eine Reihe angepasster Resampling-Funktionen vorgeschlagen,welche in Verbindung mit den entwickelten optimalen Entwurfsmethoden signifikanteQualitätssteigerungen ermöglichen.Die Vielzahl von ASRC-Strukturen sowie deren Design-Parameter bildet eine Hauptschwierigkeitbei der Auswahl eines für eine gegebene Anwendung geeigneten Verfahrens.Evaluation und Performance-Vergleiche bilden daher einen dritten Schwerpunkt. Dazu wirdzum Einen der Einfluss verschiedener Entwurfsparameter auf die erzielbare Qualität vonASRC-Algorithmen untersucht. Zum Anderen wird der benötigte Aufwand bezüglich verschiedenerPerformance-Metriken in Abhängigkeit von Design-Qualität dargestellt.Auf diese Weise sind die Ergebnisse dieser Arbeit nicht auf WFS beschränkt, sondernsind in einer Vielzahl von Anwendungen unbeschränkter Abtastratenwandlung nutzbar

Multistage adaptive filtering in a multirate digital signal processing system

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993.Includes bibliographical references (leaves 101-104).by Jen Mei Chen.Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1993

Real-Time State Estimation and Voltage Stability Assessment of Power Grids: From Theoretical Foundations to Practical Applications

The operators of power distribution systems strive to lower their operational costs and improve the quality of the power service provided to their customers. Furthermore, they are faced with the challenge of accommodating large numbers of Distributed Energy Resources (DERs) into their grids. It is expected that these problems will be tackled with a large-scale deployment of automation technology, which will enable the real-time monitoring and control of power distribution systems (i.e., similar to power transmission systems). For this purpose, real-time situation awareness w.r.t. the state and the stability of the system is needed. In view of the deployment of such automation functions into power distribution grids, there are two binding requirements. Firstly, the system models have to account for the inherent unbalances of power distribution systems (i.e., w.r.t. the components of the grid and the loads). Secondly, the analysis methods have to be real-time capable when deployed into low-cost embedded systems platforms, which are the cornerstones of automation. In other words, the analysis methods need to be computationally efficient. This thesis focuses on the modeling of unbalanced polyphase power systems, as well as the development, validation, and deployment of real-time methods for State Estimation (SE) and Voltage Stability Assessment (VSA) of such systems. More precisely, the following theoretical and practical contributions are made to the field of power system engineering. 1. Fundamental properties of the compound admittance matrix of polyphase power grids are identified. Specifically, theorems w.r.t. the rank of the compound admittance matrix, the feasibility of Kron Reduction (KR), and the existence of compound hybrid matrices are stated and formally proven. These theorems hold for generic polyphase power grids (i.e., which may be unbalanced, and have an arbitrary number of phases). 2. A Voltage Stability Index (VSI) for real-time VSA of polyphase power systems is proposed. The proposed VSI is a generalization of the well-known L-index, which is achieved by integrating more generic models of the power system components. More precisely, the grid is represented by a compound hybrid matrix, slack nodes by Thévenin equivalents, and resource nodes by polynomial load models. In this regard, the theorems mentioned under item 1 substantiate the applicability of the proposed VSI. 3. A Field-Programmable Gate Array (FPGA) implementation for real-time SE of polyphase power systems is presented. This state estimator is based on a Sequential Kalman Filter (SKF), which - in contrast to the standard Kalman Filter (KF) - is suitable for implementation in such dedicated hardware. In this respect, it is formally proven that the SKF and the standard KF are equivalent if the measurement noise variables are uncorrelated. To achieve high computational performance, the grid model is reduced through KR, and the SKF calculations on the FPGA are parallelized and pipelined. 4. The methods stated under items 1-3 are deployed into an industrial real-time controller, which is used to control a real-scale microgrid. This microgrid is equipped with a metering system composed of Phasor Measurement Units (PMUs) coupled with a Phasor Data Concentrator (PDC). The real-time capability of the developed methods is validated experimentally by measuring the latencies of the PDC-SE-VSA processing chain w.r.t. the PMU timestamps

Direct digital synthesizers : theory, design and applications

Traditional designs of high bandwidth frequency synthesizers employ the use of a phase-locked-loop (PLL). A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. Fast settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Although the principle of the DDS has been known for many years, the DDS did not play a dominant role in wideband frequency generation until recent years. Earlier DDSs were limited to produce narrow bands of closely spaced frequencies, due to limitations of digital logic and D/A-converter technologies. Recent advantages in integrated circuit (IC) technologies have brought about remarkable progress in this area. By programming the DDS, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. This is an important step towards a "software-radio" which can be used in various systems. The DDS could be applied in the modulator or demodulator in the communication systems. The applications of DDS are restricted to the modulator in the base station. The aim of this research was to find an optimal front-end for a transmitter by focusing on the circuit implementations of the DDS, but the research also includes the interface to baseband circuitry and system level design aspects of digital communication systems. The theoretical analysis gives an overview of the functioning of DDS, especially with respect to noise and spurs. Different spur reduction techniques are studied in detail. Four ICs, which were the circuit implementations of the DDS, were designed. One programmable logic device implementation of the CORDIC based quadrature amplitude modulation (QAM) modulator was designed with a separate D/A converter IC. For the realization of these designs some new building blocks, e.g. a new tunable error feedback structure and a novel and more cost-effective digital power ramp generator, were developed.reviewe