A Three Phase Scheduling for System Energy Minimization of Weakly Hard Real Time Systems

This paper aims to present a three phase scheduling algorithm that offers lesser energy consumption for weakly hard real time systems modeled with (1D55E;1D55E;1D55E;1D55E;, 1D55C;1D55C;1D55C;1D55C;) constraint. The weakly hard real time system consists of a DVS processor (frequency dependent) and peripheral devices (frequency independent) components. The energy minimization is done in three phase taking into account the preemption overhead. The first phase partitions the jobs into mandatory and optional while assigning processor speed ensuring the feasibility of the task set. The second phase proposes a greedy based preemption control technique which reduces the energy consumption due to preemption. While the third phase refines the feasible schedule received from the second phase by two methods, namely speed adjustment and delayed start. The proposed speed adjustment assigns optimal speed to each job whereas fragmented idle slots are accumulated to provide better opportunity to switch the component into sleep state by delayed start strategy as a result leads to energy saving. The simulation results and examples illustrate that our approach can effectively reduce the overall system energy consumption (especially for systems with higher utilizations) while guaranteeing the (1D55E;1D55E;1D55E;1D55E;, 1D55C;1D55C;1D55C;1D55C;) at the same time

Response Time Analysis for Thermal-Aware Real-Time Systems Under Fixed-Priority Scheduling

International audienceThis paper investigates schedulability analysis for thermal-aware real-time systems. Thermal constraints are becoming more and more critical in new generation miniaturized embedded systems, e.g. Medicals implants. As part of this work, we adapt the PFPasap algorithm proposed in [1] for energy-harvesting systems to thermal-aware ones. We prove its optimality for non-concrete1 fixed-priority task sets and propose a response-time analysis based on worst-case response-time upper bounds. We evaluate the efficacy of the proposed bounds via extensive simulation over randomly-generated task systems

Fair and efficient CPU scheduling algorithms.

No abstract available.The original print copy of this thesis may be available here: http://wizard.unbc.ca/record=b131703

Dynamic voltage scaling algorithms for soft and hard real-time system

Dynamic Voltage Scaling (DVS) has not been investigated completely for further minimizing the energy consumption of microprocessor and prolonging the operational life of real-time systems. In this dissertation, the workload prediction based DVS and the offline convex optimization based DVS for soft and hard real-time systems are investigated, respectively. The proposed algorithms of soft and hard real-time systems are implemented on a small scaled wireless sensor network (WSN) and a simulation model, respectively

Mixed Criticality Systems - A Review : (13th Edition, February 2022)

This review covers research on the topic of mixed criticality systems that has been published since Vestal’s 2007 paper. It covers the period up to end of 2021. The review is organised into the following topics: introduction and motivation, models, single processor analysis (including job-based, hard and soft tasks, fixed priority and EDF scheduling, shared resources and static and synchronous scheduling), multiprocessor analysis, related topics, realistic models, formal treatments, systems issues, industrial practice and research beyond mixed-criticality. A list of PhDs awarded for research relating to mixed-criticality systems is also included

Towards Successful Application of Phase Change Memories: Addressing Challenges from Write Operations

The emerging Phase Change Memory (PCM) technology is drawing increasing attention due to its advantages in non-volatility, byte-addressability and scalability. It is regarded as a promising candidate for future main memory. However, PCM's write operation has some limitations that pose challenges to its application in memory. The disadvantages include long write latency, high write power and limited write endurance. In this thesis, I present my effort towards successful application of PCM memory. My research consists of several optimizing techniques at both the circuit and architecture level. First, at the circuit level, I propose Differential Write to remove unnecessary bit changes in PCM writes. This is not only beneficial to endurance but also to the energy and latency of writes. Second, I propose two memory scheduling enhancements (AWP and RAWP) for a non-blocking bank design. My memory scheduling enhancements can exploit intra-bank parallelism provided by non-blocking bank design, and achieve significant throughput improvement. Third, I propose Bit Level Power Budgeting (BPB), a fine-grained power budgeting technique that leverages the information from Differential Write to achieve even higher memory throughput under the same power budget. Fourth, I propose techniques to improve the QoS tuning ability of high-priority applications when running on PCM memory. In summary, the techniques I propose effectively address the challenges of PCM's write operations. In addition, I present the experimental infrastructure in this work and my visions of potential future research topics, which could be helpful to other researchers in the area

DYNAMIC VOLTAGE SCALING FOR PRIORITY-DRIVEN SCHEDULED DISTRIBUTED REAL-TIME SYSTEMS

Energy consumption is increasingly affecting battery life and cooling for real- time systems. Dynamic Voltage and frequency Scaling (DVS) has been shown to substantially reduce the energy consumption of uniprocessor real-time systems. It is worthwhile to extend the efficient DVS scheduling algorithms to distributed system with dependent tasks. The dissertation describes how to extend several effective uniprocessor DVS schedul- ing algorithms to distributed system with dependent task set. Task assignment and deadline assignment heuristics are proposed and compared with existing heuristics concerning energy-conserving performance. An admission test and a deadline com- putation algorithm are presented in the dissertation for dynamic task set to accept the arriving task in a DVS scheduled real-time system. Simulations show that an effective distributed DVS scheduling is capable of saving as much as 89% of energy that would be consumed without using DVS scheduling. It is also shown that task assignment and deadline assignment affect the energy- conserving performance of DVS scheduling algorithms. For some aggressive DVS scheduling algorithms, however, the effect of task assignment is negligible. The ad- mission test accept over 80% of tasks that can be accepted by a non-DVS scheduler to a DVS scheduled real-time system

Dynamic Voltage Scaling for Energy- Constrained Real-Time Systems

The problem of reducing energy consumption is dominating the design of several real-time systems. The Dynamic Voltage Scaling (DVS) technique, provided by most microprocessors, allow to balance computational speed versus energy consumption. We present some novel energy-aware scheduling algorithms that allow to expoit this technique while meeting real-time constraints. In particular, we present the GRUB-PA algorithm which, unlike most existing algorithms, allows to reduce energy consumption on real-time systems consisting of any kind of task. We also present a working implementation of the algorithm on Linux