Total Dose Simulation for High Reliability Electronics

abstract: New technologies enable the exploration of space, high-fidelity defense systems, lighting fast intercontinental communication systems as well as medical technologies that extend and improve patient lives. The basis for these technologies is high reliability electronics devised to meet stringent design goals and to operate consistently for many years deployed in the field. An on-going concern for engineers is the consequences of ionizing radiation exposure, specifically total dose effects. For many of the different applications, there is a likelihood of exposure to radiation, which can result in device degradation and potentially failure. While the total dose effects and the resulting degradation are a well-studied field and methodologies to help mitigate degradation have been developed, there is still a need for simulation techniques to help designers understand total dose effects within their design. To that end, the work presented here details simulation techniques to analyze as well as predict the total dose response of a circuit. In this dissertation the total dose effects are broken into two sub-categories, intra-device and inter-device effects in CMOS technology. Intra-device effects degrade the performance of both n-channel and p-channel transistors, while inter-device effects result in loss of device isolation. In this work, multiple case studies are presented for which total dose degradation is of concern. Through the simulation techniques, the individual device and circuit responses are modeled post-irradiation. The use of these simulation techniques by circuit designers allow predictive simulation of total dose effects, allowing focused design changes to be implemented to increase radiation tolerance of high reliability electronics.Dissertation/ThesisPh.D. Electrical Engineering 201

Layout regularity metric as a fast indicator of process variations

Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

Gallium nitride-based microwave high-power heterostructure field-effect transistors

The research described in this thesis has been carried out within a joint project between the Radboud Universiteit Nijmegen (RU) and the Technische Universiteit Eindhoven (TU/e) with the title: "Performance enhancement of GaN-based microwave power amplifiers: material, device and design issues". This project has been granted by the Dutch Technology Foundation STW under project number NAF 5040. The aims of this project have been to develop the technology required to grow state-of-the-art AlGaN/GaN epilayers on sapphire and semi-insulating (s.i.) SiC substrates using metal organic chemical vapor deposition (MOCVD) and to fabricate microwave (f > 1 GHz) high-power (Pout > 10 W) heterostructure field-effect transistors (HFETs) on these epitaxial films. MOCVD growth of AlGaN/GaN epilayers and material characterization has been done within the group Applied Materials Science (AMS) of RU. Research at the Opto-Electronic Devices group (OED) of TU/e has focused on both electrical characterization of AlGaN/GaN epilayers and design, process technology development, and characterization of GaN-based HFETs and CPW passive components. Although a considerable amount of work has been done during this research with respect to processing of CPW passive components on s.i. SiC substrates, this thesis focused on active AlGaN/GaN devices only. GaN is an excellent option for high-power/high-temperature microwave applications because of its high electric breakdown field (3 MV/cm) and high electron saturation velocity (1.5 x 107 cm/s). The former is a result of the wide bandgap (3.44 eV at RT) and enables the application of high supply voltages (> 50 V), which is one of the two requirements for highpower device performance. In addition, the wide bandgap allows the material to withstand much higher operating temperatures (300oC - 500oC) than can the conventional semiconductor materials such as Si, GaAs, and InP. A big advantage of GaN over SiC is the possibility to grow heterostructures, e.g. AlGaN/GaN. The resulting two-dimensional electron gas (2DEG) at the AlGaN/GaN heterojunction serves as the conductive channel. Large drain currents (> 1 A/mm), which are the second requirement for a power device, can be achieved because of the high electron sheet densities (> 1 x 1013 cm-2) and high electron saturation velocity. These material properties clearly indicate why GaN is a very suitable candidate for next-generation microwave high-power/high-temperature applications such as high-power amplifiers (HPAs) for GSM base stations, and microwave monolithic integrated circuits (MMICs) for radar systems. In this thesis we have presented the design, technology, and measurement results of n.i.d. AlGaN/GaN:Fe HFETs grown on s.i. 4H-SiC substrates by MOCVD. These devices have submicrometer T- or FP-gates with a gate length (Lg) of 0.7 µm and total gate widths (Wg) of 0.25 mm, 0.5 mm, and 1.0 mm, respectively. The 1.0 mm devices are capable of producing a maximum microwave output power (Pout) of 11.9 W at S-band (2 GHz - 4 GHz) using class AB bias conditions of VDS = 50 V and VGS = -4.65 V. It has to be noted that excellent scaling of Pout with Wg has been demonstrated. In addition, the associated power gain (Gp) ranges between 15 dB and 20 dB, and for the power added efficiency (PAE) values from 54 % up to 70 % have been obtained. These results clearly illustrate both the successful development of the MOCVD growth process, and the successful development and integration of process modules such as ohmic and Schottky contact technology, device isolation, electron beam lithography, surface passivation, and air bridge technology, into a process flow that enables the fabrication of state-of-the-art large periphery n.i.d. AlGaN/GaN:Fe HFETs on s.i. SiC substrates, which are perfectly suitable for application in e.g. HPAs at S-band