45-nm Radiation Hardened Cache Design

abstract: Circuits on smaller technology nodes become more vulnerable to radiation-induced upset. Since this is a major problem for electronic circuits used in space applications, designers have a variety of solutions in hand. Radiation hardening by design (RHBD) is an approach, where electronic components are designed to work properly in certain radiation environments without the use of special fabrication processes. This work focuses on the cache design for a high performance microprocessor. The design tries to mitigate radiation effects like SEE, on a commercial foundry 45 nm SOI process. The design has been ported from a previously done cache design at the 90 nm process node. The cache design is a 16 KB, 4 way set associative, write-through design that uses a no-write allocate policy. The cache has been tested to write and read at above 2 GHz at VDD = 0.9 V. Interleaved layout, parity protection, dual redundancy, and checking circuits are used in the design to achieve radiation hardness. High speed is accomplished through the use of dynamic circuits and short wiring routes wherever possible. Gated clocks and optimized wire connections are used to reduce power. Structured methodology is used to build up the entire cache.Dissertation/ThesisM.S. Electrical Engineering 201

Single Event Effect Hardening Designs in 65nm CMOS Bulk Technology

Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A single particle from a radiation environment strikes semiconductor materials resulting in voltage and current perturbation, where errors are induced. This phenomenon is termed a Single Event Effect (SEE). With the shrinking of transistor size, charge sharing between adjacent devices leads to less effectiveness of current radiation hardening methods. Improving fault-tolerance of storage cells and logic gates in advanced technologies becomes urgent and important. A new Single Event Upset (SEU) tolerant latch is proposed based on a previous hardened Quatro design. Soft error analysis tools are used and results show that the critical charge of the proposed design is approximately 2 times higher than that of the reference design with negligible penalty in area, delay, and power consumption. A test chip containing the proposed flip-flop chains was designed and exposed to alpha particles as well as heavy ions. Radiation experimental results indicate that the soft error rates of the proposed design are greatly reduced when Linear Energy Transfer (LET) is lower than 4, which makes it a suitable candidate for ground-level high reliability applications. To improve radiation tolerance of combinational circuits, two combinational logic gates are proposed. One is a layout-based hardening Cascode Voltage Switch Logic (CVSL) and the other is a fault-tolerant differential dynamic logic. Results from a SEE simulation tool indicate that the proposed CVSL has a higher critical charge, less cross section, and shorter Single Event Transient (SET) pulses when compared with reference designs. Simulation results also reveal that the proposed differential dynamic logic significantly reduces the SEU rate compared to traditional dynamic logic, and has a higher critical charge and shorter SET pulses than reference hardened design

In-Circuit Mitigation Approach of Single Event Transients for 45nm Flip-Flops

Nowadays, radiation-induced Single Event Transients are a leading cause of critical errors in CMOS nanometric integrated circuits. In this work, we propose a workflow for analyzing and mitigating nanometric CMOS integrated circuits to radiation-induced transient errors. The analysis phase starts with the developed Rad-Ray tool for mimicking the passage of the radiation particles through the silicon matter of the cells to identify the features of the generated transient pulses. The tool is integrated with an electrical simulator to evaluate the dynamic behavior of the transient pulses inserted and propagated in the circuit. A tunable mitigation solution is proposed by inserting the filtering block before the storage element, tuned based on the duration and amplitude of the expected transient pulse, identified in the analysis phase. Experimental results are achieved by applying the proposed approach on the 45 nm Flip-Flop component available in the FreePDK design kit, comparing the Dynamic Error Rate for the original Flip-Flop and the mitigated one which shows a reduction of sensitivity up to 56% with respect of the original version, with negligible degradation of performances

Digital design techniques for dependable High-Performance Computing

L'abstract è presente nell'allegato / the abstract is in the attachmen

Study of Layout Techniques in Dynamic Logic Circuitry for Single Event Effect Mitigation

Dynamic logic circuits are highly suitable for high-speed applications, considering the fact that they have a smaller area and faster transition. However, their application in space or other radiation-rich environments has been significantly inhibited by their susceptibility to radiation effects. This work begins with the basic operations of dynamic logic circuits, elaborates upon the physics underlying their radiation vulnerability, and evaluates three techniques that harden dynamic logic from the layout: drain extension, pulse quenching, and a proposed method. The drain extension method adds an extra drain to the sensitive node in order to improve charge sharing, the pulse quenching scheme utilizes charge sharing by duplicating a component that offsets the transient pulse, and the proposed technique takes advantage of both. Domino buffers designed using these three techniques, along with a conventional design as reference, were modeled and simulated using a 3D TCAD tool. Simulation results confirm a significant reduction of soft error rate in the proposed technique and suggest a greater reduction with angled incidence. A 130 nm chip containing designed buffer and register chains was fabricated and tested with heavy ion irradiation. According to the experiment results, the proposed design achieved 30% soft error rate reduction, with 19%, 20%, and 10% overhead in speed, power, and area, respectively

Cross-layer Soft Error Analysis and Mitigation at Nanoscale Technologies

This thesis addresses the challenge of soft error modeling and mitigation in nansoscale technology nodes and pushes the state-of-the-art forward by proposing novel modeling, analyze and mitigation techniques. The proposed soft error sensitivity analysis platform accurately models both error generation and propagation starting from a technology dependent device level simulations all the way to workload dependent application level analysis

STUDY OF SINGLE-EVENT EFFECTS ON DIGITAL SYSTEMS

Microelectronic devices and systems have been extensively utilized in a variety of radiation environments, ranging from the low-earth orbit to the ground level. A high-energy particle from such an environment may cause voltage/current transients, thereby inducing Single Event Effect (SEE) errors in an Integrated Circuit (IC). Ever since the first SEE error was reported in 1975, this community has made tremendous progress in investigating the mechanisms of SEE and exploring radiation tolerant techniques. However, as the IC technology advances, the existing hardening techniques have been rendered less effective because of the reduced spacing and charge sharing between devices. The Semiconductor Industry Association (SIA) roadmap has identified radiation-induced soft errors as the major threat to the reliable operation of electronic systems in the future. In digital systems, hardening techniques of their core components, such as latches, logic, and clock network, need to be addressed. Two single event tolerant latch designs taking advantage of feedback transistors are presented and evaluated in both single event resilience and overhead. These feedback transistors are turned OFF in the hold mode, thereby yielding a very large resistance. This, in turn, results in a larger feedback delay and higher single event tolerance. On the other hand, these extra transistors are turned ON when the cell is in the write mode. As a result, no significant write delay is introduced. Both designs demonstrate higher upset threshold and lower cross-section when compared to the reference cells. Dynamic logic circuits have intrinsic single event issues in each stage of the operations. The worst case occurs when the output is evaluated logic high, where the pull-up networks are turned OFF. In this case, the circuit fails to recover the output by pulling the output up to the supply rail. A capacitor added to the feedback path increases the node capacitance of the output and the feedback delay, thereby increasing the single event critical charge. Another differential structure that has two differential inputs and outputs eliminates single event upset issues at the expense of an increased number of transistors. Clock networks in advanced technology nodes may cause significant errors in an IC as the devices are more sensitive to single event strikes. Clock mesh is a widely used clocking scheme in a digital system. It was fabricated in a 28nm technology and evaluated through the use of heavy ions and laser irradiation experiments. Superior resistance to radiation strikes was demonstrated during these tests. In addition to mitigating single event issues by using hardened designs, built-in current sensors can be used to detect single event induced currents in the n-well and, if implemented, subsequently execute fault correction actions. These sensors were simulated and fabricated in a 28nm CMOS process. Simulation, as well as, experimental results, substantiates the validity of this sensor design. This manifests itself as an alternative to existing hardening techniques. In conclusion, this work investigates single event effects in digital systems, especially those in deep-submicron or advanced technology nodes. New hardened latch, dynamic logic, clock, and current sensor designs have been presented and evaluated. Through the use of these designs, the single event tolerance of a digital system can be achieved at the expense of varying overhead in terms of area, power, and delay

A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor

Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead

Study of Single-Event Transient Effects on Analog Circuits

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implemented with CMOS technologies. The problem is getting worse with the technology scaling down. Radiation-hardening-by-design (RHBD) is a popular method to build CMOS devices and systems meeting performance criteria in radiation environment. Single-event transient (SET) effects in digital circuits have been studied extensively in the radiation effect community. In recent years analog RHBD has been received increasing attention since analog circuits start showing the vulnerability to the SETs due to the dramatic process scaling. Analog RHBD is still in the research stage. This study is to further study the effects of SET on analog CMOS circuits and introduces cost-effective RHBD approaches to mitigate these effects. The analog circuits concerned in this study include operational amplifiers (op amps), comparators, voltage-controlled oscillators (VCOs), and phase-locked loops (PLLs). Op amp is used to study SET effects on signal amplitude while the comparator, the VCO, and the PLL are used to study SET effects on signal state during transition time. In this work, approaches based on multi-level from transistor, circuit, to system are presented to mitigate the SET effects on the aforementioned circuits. Specifically, RHBD approach based on the circuit level, such as the op amp, adapts the auto-zeroing cancellation technique. The RHBD comparator implemented with dual-well and triple-well is studied and compared at the transistor level. SET effects are mitigated in a LC-tank oscillator by inserting a decoupling resistor. The RHBD PLL is implemented on the system level using triple modular redundancy (TMR) approach. It demonstrates that RHBD at multi-level can be cost-effective to mitigate the SEEs in analog circuits. In addition, SETs detection approaches are provided in this dissertation so that various mitigation approaches can be implemented more effectively. Performances and effectiveness of the proposed RHBD are validated through SPICE simulations on the schematic and pulsed-laser experiments on the fabricated circuits. The proposed and tested RHBD techniques can be applied to other relevant analog circuits in the industry to achieve radiation-tolerance

Fault Tolerant Electronic System Design

Due to technology scaling, which means reduced transistor size, higher density, lower voltage and more aggressive clock frequency, VLSI devices may become more sensitive against soft errors. Especially for those devices used in safety- and mission-critical applications, dependability and reliability are becoming increasingly important constraints during the development of system on/around them. Other phenomena (e.g., aging and wear-out effects) also have negative impacts on reliability of modern circuits. Recent researches show that even at sea level, radiation particles can still induce soft errors in electronic systems. On one hand, processor-based system are commonly used in a wide variety of applications, including safety-critical and high availability missions, e.g., in the automotive, biomedical and aerospace domains. In these fields, an error may produce catastrophic consequences. Thus, dependability is a primary target that must be achieved taking into account tight constraints in terms of cost, performance, power and time to market. With standards and regulations (e.g., ISO-26262, DO-254, IEC-61508) clearly specify the targets to be achieved and the methods to prove their achievement, techniques working at system level are particularly attracting. On the other hand, Field Programmable Gate Array (FPGA) devices are becoming more and more attractive, also in safety- and mission-critical applications due to the high performance, low power consumption and the flexibility for reconfiguration they provide. Two types of FPGAs are commonly used, based on their configuration memory cell technology, i.e., SRAM-based and Flash-based FPGA. For SRAM-based FPGAs, the SRAM cells of the configuration memory highly susceptible to radiation induced effects which can leads to system failure; and for Flash-based FPGAs, even though their non-volatile configuration memory cells are almost immune to Single Event Upsets induced by energetic particles, the floating gate switches and the logic cells in the configuration tiles can still suffer from Single Event Effects when hit by an highly charged particle. So analysis and mitigation techniques for Single Event Effects on FPGAs are becoming increasingly important in the design flow especially when reliability is one of the main requirements