ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究

本研究は、半導体上に集積されたアナログ・ディジタル・メモリ回路から構成されるミクストシグナルシステムを別の製造プロセスへ移行することをポーティングとして定義し、効率的なポーティングを行うための設計方式と自動回路合成アルゴリズムを提案し、いくつかの典型的な回路に対する設計事例を示し、提案手法の妥当性を立証している。北九州市立大

A Review of Bayesian Methods in Electronic Design Automation

The utilization of Bayesian methods has been widely acknowledged as a viable solution for tackling various challenges in electronic integrated circuit (IC) design under stochastic process variation, including circuit performance modeling, yield/failure rate estimation, and circuit optimization. As the post-Moore era brings about new technologies (such as silicon photonics and quantum circuits), many of the associated issues there are similar to those encountered in electronic IC design and can be addressed using Bayesian methods. Motivated by this observation, we present a comprehensive review of Bayesian methods in electronic design automation (EDA). By doing so, we hope to equip researchers and designers with the ability to apply Bayesian methods in solving stochastic problems in electronic circuits and beyond.Comment: 24 pages, a draft version. We welcome comments and feedback, which can be sent to [email protected]

Chemical Current-Conveyor: a new approach in biochemical computation

Biochemical sensors that are low cost, small in size and compatible with integrated circuit technology play an essential part in the drive towards personalised healthcare and the research described in this thesis is concerned with this area of medical instrumentation. A new biochemical measurement system able to sense key properties of biochemical fluids is presented. This new integrated circuit biochemical sensor, called the Chemical Current-Conveyor, uses the ion sensitive field effect transistor as the input sensor combined with the current-conveyor, an analog building-block, to produce a range of measurement systems. The concept of the Chemical Current-Conveyor is presented together with the design and subsequent fabrication of a demonstrator integrated circuit built on conventional 0.35μm CMOS silicon technology. The silicon area of the Chemical Current-Conveyor is (92μm x 172μm) for the N-channel version and (99μm x 165μm) for the P-channel version. Power consumption for the N-channel version is 30μW and 43μW for the P-channel version with a full load of 1MΩ. The maximum sensitivity achieved for pH measurement was 46mV per pH. The potential of the Chemical Current Conveyor as a versatile biochemical integrated circuit, able to produce output information in an appropriate form for direct clinical use has been confirmed by applications including measurement of (i) pH, (ii) buffer index ( ), (iii) urea, (iv) creatinine and (v) urea:creatinine ratio. In all five cases the device has been demonstrated successfully, confirming the validity of the original aim of this research project, namely to produce a versatile and flexible analog circuit for many biochemical measurement applications. Finally, the thesis closes with discussion of another potential application area for the Chemical Current Conveyor and the main contributions can be summarised by the design and development of the first: ISFET based current-conveyor biochemical sensor, called 'Chemical Current Conveyor, CCCII+' has been designed and developed. It is a general purpose biochemical analog building-block for several biochemical measurements. Real-time buffer capacity measurement system, based on the CCCII+, which exploits the imbedded analog computation capability of the CCCII+. Real-time enzyme based CCCII+ namely, Creatinine-CCCII+ and Urea-CCCII+ for real-time monitoring system of renal system. The system can provide outputs of 3 important parameters of the renal system, namely (i) urea concentration, (ii) creatinine concentration, and (ii) urea to creatinine ratio

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry

Development of an image converter of radical design

A long term investigation of thin film sensors, monolithic photo-field effect transistors, and epitaxially diffused phototransistors and photodiodes to meet requirements to produce acceptable all solid state, electronically scanned imaging system, led to the production of an advanced engineering model camera which employs a 200,000 element phototransistor array (organized in a matrix of 400 rows by 500 columns) to secure resolution comparable to commercial television. The full investigation is described for the period July 1962 through July 1972, and covers the following broad topics in detail: (1) sensor monoliths; (2) fabrication technology; (3) functional theory; (4) system methodology; and (5) deployment profile. A summary of the work and conclusions are given, along with extensive schematic diagrams of the final solid state imaging system product

Multi-kw dc power distribution system study program

The first phase of the Multi-kw dc Power Distribution Technology Program is reported and involves the test and evaluation of a technology breadboard in a specifically designed test facility according to design concepts developed in a previous study on space vehicle electrical power processing, distribution, and control. The static and dynamic performance, fault isolation, reliability, electromagnetic interference characterisitics, and operability factors of high distribution systems were studied in order to gain a technology base for the use of high voltage dc systems in future aerospace vehicles. Detailed technical descriptions are presented and include data for the following: (1) dynamic interactions due to operation of solid state and electromechanical switchgear; (2) multiplexed and computer controlled supervision and checkout methods; (3) pulse width modulator design; and (4) cable design factors

Sub-1 V, 4 nA CMOS voltage references with digitally-trimmable temperature coefficient

Voltage references are fundamental to mixed signal converters which are widely used in elec- tronics. Hence there are signicant advantages in having the voltage reference operate with less power while minimizing area consumption and maintaining performance. Past designs have suered from issues related to process variations which adversely aect the temperature coe- cient of the circuit output. To compensate for these process variations, a means to modify the temperature coecient are proposed and experimentally veried with two circuit architectures. Five test chip samples implement these architectures in a 0.35 m CMOS process. Design methodologies for both architectures are presented. Design techniques include the use of a high-swing cascode to improve Line Sensitivity while minimizing additional power consumption, accounting for a well-matched layout, and the eect of leakage currents on the performance of the circuit. Layout schematics, performance gures, test methodologies and results are presented. Each circuit dissipates less than 4 nW and operates down to 0.9 V or better with Line Sensitivity and Power Supply Rejection Ratio of less than 0.15 %/V and -58 dB respectively, while consuming an area of 0.053 mm2 or less. The experimental average and median temperature coecient was less than 26 ppm/C and 22 ppm/C respectively in the 􀀀20 C to 80 C range, with the best performance being less than 8.1 ppm/C. Areas of improvement and potential areas of future research are then identied to facilitate advancement of this work

An RF LC Q-enhanced CMOS iter using integrated inductors with layout optimization

Dissertação apresentada para obtenção do Grau de Mestre em Engenharia Electrotécnica e de Computadores, pela Universidade Nova de Lisboa, Faculdade de Ciências e TecnologiaThe advancement of CMOS technology led to the integration of more complex functions in a single chip. In the particular of wireless transceivers, integrated LC tanks are becoming popular both for VCOs and integrated lters. The design of a 2nd order CMOS 0.13 m Q-enhanced integrated LC lter for a frequency of 2.44 GHz is presented. The intent of this lter is to create a circuit for integrated wireless receiver and minimize the requirement for o -chip passive lter components, reducing the overall component count and size of wireless devices and systems. For RF applications the main challenge is still the design of integrated inductors with the maximum quality factor. For that purpose, tapered, i.e, variable width inductors have been introduced in the literature. In this work, a characterization of variable width integrated inductors is proposed. This inductor model is then integrated into an optimization procedure where inductors with a quality factor improvement are obtained