Retiming with wire delay and post-retiming register placement.

Tong Ka Yau Dennis.Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.Includes bibliographical references (leaves 77-81).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Motivations --- p.1Chapter 1.2 --- Progress on the Problem --- p.2Chapter 1.3 --- Our Contributions --- p.3Chapter 1.4 --- Thesis Organization --- p.4Chapter 2 --- Background on Retiming --- p.5Chapter 2.1 --- Introduction --- p.5Chapter 2.2 --- Preliminaries --- p.7Chapter 2.3 --- Retiming Problem --- p.9Chapter 3 --- Literature Review on Retiming --- p.10Chapter 3.1 --- Introduction --- p.10Chapter 3.2 --- The First Retiming Paper --- p.11Chapter 3.2.1 --- """Retiming Synchronous Circuitry""" --- p.11Chapter 3.3 --- Important Extensions of the Basic Retiming Algorithm --- p.14Chapter 3.3.1 --- """A Fresh Look at Retiming via Clock Skew Optimization""" --- p.14Chapter 3.3.2 --- """An Improved Algorithm for Minimum-Area Retiming""" --- p.16Chapter 3.3.3 --- """Efficient Implementation of Retiming""" --- p.17Chapter 3.4 --- Retiming in Physical Design Stages --- p.19Chapter 3.4.1 --- """Physical Planning with Retiming""" --- p.19Chapter 3.4.2 --- """Simultaneous Circuit Partitioning/Clustering with Re- timing for Performance Optimization" --- p.20Chapter 3.4.3 --- """Performance Driven Multi-level and Multiway Parti- tioning with Retiming" --- p.22Chapter 3.5 --- Retiming with More Sophisticated Timing Models --- p.23Chapter 3.5.1 --- """Retiming with Non-zero Clock Skew, Variable Register, and Interconnect Delay""" --- p.23Chapter 3.5.2 --- """Placement Driven Retiming with a Coupled Edge Tim- ing Model""" --- p.24Chapter 3.6 --- Post-Retiming Register Placement --- p.26Chapter 3.6.1 --- """Layout Driven Retiming Using the Coupled Edge Tim- ing Model""" --- p.26Chapter 3.6.2 --- """Integrating Logic Retiming and Register Placement""" --- p.27Chapter 4 --- Retiming with Gate and Wire Delay [2] --- p.29Chapter 4.1 --- Introduction --- p.29Chapter 4.2 --- Problem Formulation --- p.30Chapter 4.3 --- Optimal Approach [2] --- p.31Chapter 4.3.1 --- Original Mathematical Framework for Retiming --- p.31Chapter 4.3.2 --- A Modified Optimal Approach --- p.33Chapter 4.4 --- Near-Optimal Fast Approach [2] --- p.37Chapter 4.4.1 --- Considering Wire Delay Only --- p.38Chapter 4.4.2 --- Considering Both Gate and Wire Delay --- p.42Chapter 4.4.3 --- Computational Complexity --- p.43Chapter 4.4.4 --- Experimental Results --- p.44Chapter 4.5 --- Lin's Optimal Approach [23] --- p.47Chapter 4.5.1 --- Theoretical Results --- p.47Chapter 4.5.2 --- Algorithm Description --- p.51Chapter 4.5.3 --- Computational Complexity --- p.52Chapter 4.5.4 --- Experimental Results --- p.52Chapter 4.6 --- Summary --- p.54Chapter 5 --- Register Insertion in Placement [36] --- p.55Chapter 5.1 --- Introduction --- p.55Chapter 5.2 --- Problem Formulation --- p.57Chapter 5.3 --- Placement of Registers After Retiming --- p.60Chapter 5.3.1 --- Topology Finding --- p.60Chapter 5.3.2 --- Register Placement --- p.69Chapter 5.4 --- Experimental Results --- p.71Chapter 5.5 --- Summary --- p.74Chapter 6 --- Conclusion --- p.75Bibliography --- p.7

Custom Integrated Circuits

Contains reports on seven research projects.U.S. Air Force - Office of Scientific Research (Contract F49620-84-C-0004)National Science Foundation (Grant ECS81-18160)Defense Advanced Research Projects Agency (Contract NOO14-80-C-0622)National Science Foundation (Grant ECS83-10941

Energy-Efficient Digital Circuit Design using Threshold Logic Gates

abstract: Improving energy efficiency has always been the prime objective of the custom and automated digital circuit design techniques. As a result, a multitude of methods to reduce power without sacrificing performance have been proposed. However, as the field of design automation has matured over the last few decades, there have been no new automated design techniques, that can provide considerable improvements in circuit power, leakage and area. Although emerging nano-devices are expected to replace the existing MOSFET devices, they are far from being as mature as semiconductor devices and their full potential and promises are many years away from being practical. The research described in this dissertation consists of four main parts. First is a new circuit architecture of a differential threshold logic flipflop called PNAND. The PNAND gate is an edge-triggered multi-input sequential cell whose next state function is a threshold function of its inputs. Second a new approach, called hybridization, that replaces flipflops and parts of their logic cones with PNAND cells is described. The resulting \hybrid circuit, which consists of conventional logic cells and PNANDs, is shown to have significantly less power consumption, smaller area, less standby power and less power variation. Third, a new architecture of a field programmable array, called field programmable threshold logic array (FPTLA), in which the standard lookup table (LUT) is replaced by a PNAND is described. The FPTLA is shown to have as much as 50% lower energy-delay product compared to conventional FPGA using well known FPGA modeling tool called VPR. Fourth, a novel clock skewing technique that makes use of the completion detection feature of the differential mode flipflops is described. This clock skewing method improves the area and power of the ASIC circuits by increasing slack on timing paths. An additional advantage of this method is the elimination of hold time violation on given short paths. Several circuit design methodologies such as retiming and asynchronous circuit design can use the proposed threshold logic gate effectively. Therefore, the use of threshold logic flipflops in conventional design methodologies opens new avenues of research towards more energy-efficient circuits.Dissertation/ThesisDoctoral Dissertation Computer Science 201

Broadening the Scope of Multi-Objective Optimizations in Physical Synthesis of Integrated Circuits.

In modern VLSI design, physical synthesis tools are primarily responsible for satisfying chip-performance constraints by invoking a broad range of circuit optimizations, such as buffer insertion, logic restructuring, gate sizing and relocation. This process is known as timing closure. Our research seeks more powerful and efficient optimizations to improve the state of the art in modern chip design. In particular, we integrate timing-driven relocation, retiming, logic cloning, buffer insertion and gate sizing in novel ways to create powerful circuit transformations that help satisfy setup-time constraints. State-of-the-art physical synthesis optimizations are typically applied at two scales: i) global algorithms that affect the entire netlist and ii) local transformations that focus on a handful of gates or interconnections. The scale of modern chip designs dictates that only near-linear-time optimization algorithms can be applied at the global scope — typically limited to wirelength-driven placement and legalization. Localized transformations can rely on more time-consuming optimizations with accurate delay models. Few techniques bridge the gap between fully-global and localized optimizations. This dissertation broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales. In particular, we integrate groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima. Integrated transformations in this dissertation are developed by identifying and removing obstacles to successful optimizations. Integration is achieved through mapping multiple operations to rigorous mathematical optimization problems that can be solved simultaneously. We achieve computational scalability in our techniques by leveraging analytical delay models and focusing optimization efforts on carefully selected regions of the chip. In this regard, we make extensive use of a linear interconnect-delay model that accounts for the impact of subsequent repeated insertion. Our integrated transformations are evaluated on high-performance circuits with over 100,000 gates. Integrated optimization techniques described in this dissertation ensure graceful timing-closure process and impact nearly every aspect of a typical physical synthesis flow. They have been validated in EDA tools used at IBM for physical synthesis of high-performance CPU and ASIC designs, where they significantly improved chip performance.Ph.D.Computer Science & EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/78744/1/iamyou_1.pd