Scalable Multiple Patterning Layout Decomposition Implemented by a Distribution Evolutionary Algorithm

As the feature size of semiconductor technology shrinks to 10 nm and beyond, the multiple patterning lithography (MPL) attracts more attention from the industry. In this paper, we model the layout decomposition of MPL as a generalized graph coloring problem, which is addressed by a distribution evolutionary algorithm based on a population of probabilistic model (DEA-PPM). DEA-PPM can strike a balance between decomposition results and running time, being scalable for varied settings of mask number and lithography resolution. Due to its robustness of decomposition results, this could be an alternative technique for multiple patterning layout decomposition in next-generation technology nodes

Lithography aware physical design and layout optimization for manufacturability

textAs technology continues to scale down, semiconductor manufacturing with 193nm lithography is greatly challenging because the required half pitch size is beyond the resolution limit. In order to bridge the gap between design requirements and manufacturing limitations, various resolution enhancement techniques have been proposed to avoid potentially problematic patterns and to improve product yield. In addition, co-optimization between design performance and manufacturability can further provide flexible and significant yield improvement, and it has become necessary for advanced technology nodes. This dissertation presents the methodologies to consider the lithography impact in different design stages to improve layout manufacturability. Double Patterning Lithography (DPL) has been a promising solution for sub-22nm node volume production. Among DPL techniques, self-aligned double patterning (SADP) provides good overlay controllability when two masks are not aligned perfectly. However, SADP process places several limitations on design flexibility and still exists many challenges in physical design stages. Starting from the early design stage, we analyze the standard cell designs and construct a set of SADP-aware cell placement candidates, and show that placement legalization based on this SADP awareness information can effectively resolve DPL conflicts. In the detailed routing stage, we propose a new routing cost formulation based on SADP-compliant routing guidelines, and achieve routing and layout decomposition simultaneously. In the case that limited routing perturbation is allowed, we propose a post-routing flow based on lithography simulation and lithography-aware design rules. Both routing methods, one in detailed routing stage and one in post routing stage, reduce DPL conflicts/violations significantly with negligible wire length impact. In the layout decomposition stage, layout modification is restricted and thus the manufacturability is even harder to guaranteed. By taking the advantage of complementary lithography, we present a new layout decomposition approach with e-beam cutting, which optimizes SADP overlay error and e-beam lithography throughput simultaneously. After the mask layout is defined, optical proximity correction (OPC) is one of the resolution enhancement techniques that is commonly required to compensate the image distortion from the lithography process. We propose an inverse lithography technique to solve the OPC problem considering design target and process window co-optimization. Our mask optimization is pixel based and thus can enable better contour fidelity. In the final physical verification stage, a complex and time-consuming lithography simulation needs to be performed to identify faulty patterns. We provide a classification method based on support vector machine and principle component analysis that detects lithographic hotspots efficiently and accurately.Electrical and Computer Engineerin

Algorithms for DFM in electronic design automation

As the dimension of features in integrated circuits (IC) keeps shrinking to fulfill Moore’s law, the manufacturing process has no choice but confronting the limit of physics at the expense of design flexibility. On the other hand, IC designs inevitably becomes more complex to meet the increasing demand of computational power. To close this gap, design for manufacturing (DFM) becomes the key to enable an easy and low-cost IC fabrication. Therefore, efficient electronic design automation (EDA) algorithms must be developed for DFM to address the design constraints and help the designers to better facilitate the manufacture process. As the core of manufacturing ICs, conventional lithography systems (193i) reach their limit for the 22 nm technology node and beyond. Consequently, several advanced lithography techniques are proposed, such as multiple patterning lithography (MPL), extreme ultra-violet lithography (EUV), electron beam (E-beam), and block copolymer directed self-assembly (DSA); however, DFM algorithms are essential for them to achieve better printability of a design. In this dissertation, we focus on analyzing the compatibility of designs and various advanced lithography techniques, and develop efficient algorithms to enable the manufacturing. We first explore E-Beam, one of the promising candidates for IC fabrication beyond the 10 nm technology node. To address its low throughput issue, the character projection technique has been proposed, and its stencil planning can be optimized with an awareness of overlapping characters. 2D stencil planning is proved NP-Hard. With the assumption of standard cells, the 2D problem can be partitioned into 1D row ordering subproblems; however, it is also considered hard, and no efficient optimal solution has been provided so far. We propose a polynomial time optimal algorithm to solve the 1D row ordering problem, which serves as the major subroutine for the entire stencil planning problem. Technical proofs and experimental results verify that our algorithm is efficient and indeed optimal. As the most popular and practical lithography technique, MPL utilizes multiple exposures to print a single layout and thus allows placement of features within the minimum distance. Therefore, a feasible decomposition of the layout is a must to adopt MPL, and it is usually formulated as a graph k-coloring problem, which is computationally difficult for k > 2. We study the k-colorability of rectangular and diagonal grid graphs as induced subgraphs of a rectangular or diagonal grid respectively, since it has direct applications in printing contact/via layouts. It remains an open question on how hard it is to color grid graphs due to their regularity and sparsity. In this dissertation, we conduct a complete analysis of the k-coloring problems on rectangular and diagonal grid graphs, and particularly the NP-completeness of 3-coloring on a diagonal grid graph is proved. In practice, we propose an exact 3-coloring algorithm for those graphs and conduct experiments to verify its performance and effectiveness. Besides, we also develop an efficient algorithm for model based MPL, because it is more expensive but accurate than the rule based decomposition. As one of the alternative lithography techniques, block copolymer directed self-assembly (DSA) is studied. It has emerged as a low-cost, high- throughput option in the pursuit of alternatives to traditional optical lithography. However, issues of defectivity have hampered DSA’s viability for large-scale patterning. Recent studies have shown the copolymer fill level to be a crucial factor in defectivity, as template overfill can result in malformed DSA structures and poor LCDU after etching. For this reason, the use of sub-DSA resolution assist features (SDRAFs) as a method of evening out template density has been demonstrated. In this dissertation, we propose an algorithm to place SDRAFs in random logic contact/via layouts. By adopting this SDRAF placement scheme, we can significantly improve the density unevenness and the resources used are also optimized. We also apply our knowledge in coloring grid graphs to the problem of group-and-coloring in DSA-MPL hybrid lithography. We derive a solution to group-3-coloring and prove the NP-completeness of grouping-2-coloring

Design automation algorithms for advanced lithography

In circuit manufacturing, as the technology nodes keep shrinking, conventional 193 nm immersion lithography (193i) has reached its printability limit. To continue the scaling with Moore's law, different kinds of advanced lithography have been proposed, such as multiple patterning lithography (MPL), extreme ultraviolet (EUV), electron beam lithography (EBL) and directed self-assembly (DSA). While these new technologies create enormous opportunities, they also pose great design challenges due to their unique process characteristics and stringent constraints. In order to smoothly adopt these advanced lithography technologies in integrated circuit (IC) fabrication, effective electronic design automation (EDA) algorithms must be designed and integrated into computer-aided design (CAD) tools to address the underlying design constraints and help the circuit designer to better facilitate the lithography process. In this thesis, we focus on algorithmic design and efficient implementation of EDA algorithm for advanced lithography, including directed self-assembly (DSA) and self-aligned double patterning (SADP), to conquer the physical challenges and improve the manufacturing yield. The first advanced lithography technology we explore is self-aligned double patterning (SADP). SADP has the significant advantage over traditional litho-etch-litho-etch (LELE) double patterning in its ability to eliminate overlay, making it a preferable DPL choice for the 14 nm technology node. As in any DPL technology, layout decomposition is the key problem. While the layout decomposition problem for LELE DPL has been well studied in the literature, only a few attempts have been made for the SADP layout decomposition problem. This thesis studies the SADP decomposition problem in different scenarios. SADP has been successfully deployed in 1D patterns and has several applications; however, applying it to 2D patterns turns out to be much more difficult. All previous exact algorithms were based on computationally expensive methods such as SAT or ILP. Other previous algorithms were heuristics without a guarantee that an overlay-free solution can be found even if one exists. The SADP decomposition problem on general 2D layout is proven to be NP-complete. However, we show that if we restrict the overlay, the problem is polynomial-time solvable, and present an exact algorithm to determine if a given 2D layout has a no-overlay SADP decomposition. When designing the layout decomposition algorithms, it is usually useful to take the layout structure into consideration. As most of the current IC layouts adopt a row-based standard cell design style, we can take advantage of its characteristics and design more efficient algorithms compared to the algorithms for general 2D patterns. In particular, the fixed widths of standard cells and power tracks on top and bottom of cells suggest that improvements can be made over the algorithms for general decomposition problem. We present a shortest-path based polynomial time SADP decomposition algorithm for row-based standard cell layout that efficiently finds decompositions with minimum overlay violations. Our proposed algorithm takes advantage of the fixed width of the cells and the alternating power tracks between the rows to limit the possible decompositions and thus achieve high efficiency. The next advanced lithography technology we discuss in the thesis is directed self-assembly (DSA). Block copolymer directed self-assembly (DSA) is a promising technique for patterning contact holes and vias in 7 nm technology nodes. To pattern contacts/vias with DSA, guiding templates are usually printed first with conventional lithography (193i) that has a coarser pitch resolution. Contact holes are then patterned with DSA process. The guiding templates play the role of defining the DSA patterns, which have a finer resolution than the templates. As a result, different patterns can be obtained through controlling the templates. It is shown that DSA lithography is very promising in patterning contacts/vias in 7 nm technology node. However, to utilize DSA for full-chip manufacturing, EDA for DSA must be fully explored because EDA is the key enabler for manufacturing, and the EDA research for DSA is still lagging behind. To pattern the contact layer with DSA, we must ensure that all the contacts in the layout require only feasible DSA templates. Nevertheless, the original layout may not be designed in a DSA-friendly way. However, even with an optimized library, infeasible templates may be introduced after the physical design phase. We propose a simulated-annealing (SA) based scheme to perform full-chip level contact layer optimization. According to the experimental results, the DSA conflicts in the contact layer are reduced by close to 90% on average after applying the proposed optimization algorithm. It is a current trend that industry is transiting from the random 2D designs to highly regular 1D gridded designs for sub-20 nm nodes and fabricating circuit designs with print-cut technology. In this process, the randomly distributed cuts may be too dense to be printed by single patterning lithography. DSA has proven its success in contact hole patterning, and can be easily expanded to cut printing for 1D gridded designs. Nevertheless, the irregular distribution of cuts still presents a great challenge for DSA, as the self-assembly process usually forms regular patterns. As a result, the cut layer must be optimized for the DSA process. To address the above problem, we propose an efficient algorithm to optimize cut layers without hurting the original circuit logic. Our work utilizes a technique called `line-end extension' to move the cuts and extend the functional wires without changing the original functionality of the circuit. Consequently, the cuts can be redistributed and grouped into valid DSA templates. Multiple patterning lithography has been widely adopted for today's circuit manufacturing. However, increasing the number of masks will make the manufacturing process more expensive. By incorporating DSA into the multiple patterning process, it is possible to reduce the number of masks and achieve a cost-effective solution. We study the decomposition problem for the contact layer in row-based standard cell layout with DSA-MP complementary lithography. We explore several heuristic-based approaches, and propose an algorithm that decomposes a standard cell row optimally in polynomial-time. Our experiments show that our algorithm is guaranteed to find a minimum cost solution if one exists, while the heuristic cannot or only finds a sub-optimal solution. Our results show that the DSA-MP complementary approach is very promising for the future advanced nodes. As in any lithography technique, the process variation control and proximity correction are the most important issues. As the DSA templates are patterned by conventional lithography, the patterned templates are prone to deviate from mask shapes due to process variations, which will ultimately affect the contacts after the DSA process even for the same type of template. Therefore, in order to enable the DSA technology in contact/via layer printing, it is extremely important to accurately model and detect hotspots, as well as estimate the contact pitch and locations during the verification phase. We propose a machine learning based design automation framework for DSA verification. A novel DSA model and a set of features are included. We implemented the proposed ML-based flow and performed extensive experiments on comparing the performances of learning algorithms and features. The experimental results show that our approach is much more efficient than the traditional approach, and can produce highly accurate results

Alternative Lithographic Methods for Variable Aspect Ratio Vias

The foundation of semiconductor industry has historically been driven by scaling. Device size reduction is enabled by increased pattern density, enhancing functionality and effectively reducing cost per chip. Aggressive reductions in memory cell size have resulted in systems with diminishing area between parallel bit/word lines. This affords an even greater challenge in the patterning of contact level features that are inherently difficult to resolve because of their relatively small area, a product of their two domain critical dimension image. To accommodate these trends there has been a shift toward the implementation of elliptical contact features. This empowers designers to maximize the use of free space between bit/word lines and gate stacks while preserving contact area; effectively reducing the minor via axis dimension while maintaining a patternable threshold in increasingly dense circuitry. It is therefore critical to provide methods that enhance the resolving capacity of varying aspect ratio vias for implementation in electronic design systems. This work separately investigates two unique, non-traditional lithographic techniques in the integration of an optical vortex mask as well as a polymer assembly system as means to augment ellipticity while facilitating contact feature scaling. This document affords a fundamental overview of imaging theory, details previous literature as to the technological trends enabling the resolving of contact features and demonstrates simulated & empirical evidence that the described methods have great potential to extend the resolution of variable aspect ratio vias using lithographic technologies

Resolution enhancement in mask aligner photolithography

Photolithographie ist eine unentbehrliche Technologie in der heutigen Mikrofabrikation integrierter elektronischer Schaltungen und optischer Komponenten auf verschiedenen Größenskalen. Die zugrundeliegende Aufgabe ist die Replikation der gewünschten Struktur, die kodiert ist in einer Photomaske, auf einem photolackbedeckten Wafer. In vergangenen Jahrzehnten gab es eine beeindruckende Weiterentwicklung photolithographischer Anlagen, was Auflösungen weit unterhalb eines Mikrometers ermöglicht. Das einfachste photolithographische Instrument ist der Maskenjustierbelichter, bei dem die Photomaske und der Wafer entweder in Kontakt oder in unmittelbare Nähe gebracht werden (Proximity-Modus), ohne zusätzliche optische Komponenten dazwischen. Vor über 50~Jahren eingeführt bleibt der Maskenjustierbelichter aufgrund seines wirtschaftlichen Betriebs das Instrument der Wahl für die Herstellung unkritischer Schichten, mit einer Auflösung von einigen Mikrometern im bevorzugten Proximity-Modus. Maskenjustierbelichter werden beispielsweise für die Herstellung von Mikrolinsen, lichtemittierende Dioden und mikromechanischen Systemen verwendet. Die erreichbare laterale räumliche Auflösung ist letztlich begrenzt durch die Beugung des Lichts an den Strukturen der Photomaske, was zu Verfälschungen der Abbildung auf dem Photolack führt. In dieser Arbeit entwickeln, präsentieren und diskutieren wir mehrere Technologien zur Auflösungsverbesserung für Maskenjustierbelichter im Proximity-Modus. Dies umfasst Photolithographie mit einer neuartigen Lichtquelle, die im tiefen Ultraviolett-Bereich emittiert, eine rigoros optimierte Phasenschiebermaske für periodische Strukturen, optische Proximity-Korrektur (Nahbereichskorrektur) angewandt auf nichtorthogonale Geometrien, und die Anwendung optischer Metaoberflächen als Photomasken. Eine Reduzierung der Wellenlänge verringert die Auswirkungen der Lichtbrechung und verbessert daher direkt die Auflösung, benötigt aber auch die Entwicklung geeigneter Konzepte für die Strahlformung und Homogenisierung der Beleuchtung. Wir diskutieren die Integration einer neuartigen Lichtquelle, ein frequenzvervierfachter Dauerstrichlaser mit einer Emissionswellenlänge von 193$\,$nm, in einem Maskenjustierbelichter. Damit zeigen wir erfolgreiche Prints von Teststrukturen mit einer Auflösung von bis zu 1,75$\,$µm bei einem Proximity-Abstand von 20$\,$µm. Bei Verwendung des selbstabbildenden Talboteffekts wird sogar eine Auflösung weit unterhalb eines Mikrometers für periodische Strukturen erzielt. Außerdem diskutieren wir die rigorose Simulation und Optimierung der Lichtausbreitung in und hinter Phasenschiebermasken, die unter schrägem Einfall belichtet werden. Mit einem optimierten Photomaskendesign kann dabei die Periode bei Belichtung unter drei diskreten Winkeln verkleinert abgebildet werden. Dies erlaubt es, Strukturen deutlich kleiner als ein Mikrometer abzubilden, wobei die Strukturen auf der Photomaske deutlich größer und damit einfacher herzustellen sind. Zudem betrachten wir eine Simulations- und Optimierungsmethode für die optische Proximity-Korrektur nicht-orthogonaler Strukturen, was deren Formtreue verbessert. die Wirksamkeit beider Konzepte bestätigen wir erfolgreich in experimentellen Prints. Die Verwendung optischer Metaoberflächen erweitert die Fähigkeiten zur Wellenfrontformung von Photomasken gegenüber etablierten Intensitäts- oder Phasenschiebermasken. Wir diskutieren zwei Designs für optische Metaoberflächen, die beide den vollen $2\,\pi$-Phasenbereich abdecken. Ein Design beinhaltet dabei noch einen plasmonischen Absorber, was zusätzliche Möglichkeiten bietet, den Transmissionskoeffizient anzupassen. Desweiteren beschreiben wir einen Algorithmus zur Berechnung des Maskenlayouts für beliebige Strukturen. Eine kontinuierliche Weiterentwicklung von Maskenjustierbelichtern ist unerlässlich, um Schritt zu halten mit der fortschreitenden Miniaturisierung in allen Bereich der Optik, der Mechanik und der Elektronik. Unsere Forschungsergebnisse ermöglichen es, die Auflösung der optischen Lithographie im Proximity-Modus zu verbessern und sich damit den zukünftigen Herausforderungen der optischen Industrie stellen zu können

Reduction of Line Edge Roughness (LER) in Interference-Like Large Field Lithography

Line edge roughness (LER) is seen as one of the most crucial challenges to be addressed in advanced technology nodes. In order to alleviate it, several options were explored in this work for the interference-like lithography imaging conditions. The most straight forward option was to scale interference lithography (IL) for large field integrated circuit (IC) applications. IL not only serves as a simple method to create high resolution period patterns, but, it also provides the highest theoretical contrast achievable compared to other optical lithography systems. Higher contrast yields a smaller transition region between the low and high intensity parts of the image, therefore, inherently lowers LER. Two of the challenges that would prohibit scaling IL for large field IC applications were addressed in this work: (1) field size limitations, and (2) magnification correction (i.e., pitch fine-tuning) ability. Experimental results showed less than 0.5 nm pitch adjustment capability using fused silica wedges mounted on rotational stages at 300 nm pitch pattern. A detailed discussion on maximum practical IL field size was outlined by considering the subsequent trim exposures and optical path difference effects between the interfering diffraction orders. The practical limit on the IL field size was assessed to be 10 mm for the conditions specified in this work. One of the contributors of LER is the mask absorber roughness. To mitigate it, two methods were explored that are also applicable to scanners working under interference-like conditions: (1) aerial image averaging via directional translation, and (2) pupil plane filtering. Experiments on pupil plane filtering approach were performed at Imec in Leuven, Belgium, on the ASML:NXT1950i scanner equipped with FlexWAVE wavefront manipulator. Utilizing an optimized phase filter at the pupil plane and a programmed roughness mask, the transfer of 200 nm roughness period to the wafer plane was eliminated. This mitigation effect was found to be strongly dependent on the focus