Laser via generation into flexible substrates

The microelectronics industry is moving toward smaller feature sizes. The main driving forces are to improve performance and to lower cost. From the performance point of view the small distances between chips together with the short interconnection routes have of great importance in order to achieve faster operation. The application of polymeric materials for the insulating and protective layers of interconnect substrates is beneficial to the performance and to the cost of a circuit module as well. An advanced technology for the fabrication of very high density interconnects applies microvia flexible substrates. This technology has particular significance for the interposers of chip scale packages. Laser processing of polymeric materials applied for via generation, image transfer, contour cutting, etc. has proved to be an efficient tool for the fabrication of interconnect substrates. The paper describes some results of a research project that aims at the application Of CO2 and frequency multiplied Nd:YAG lasers for drilling via holes into copper clad flexible laminates of polyimide, epoxy and polyester base materials. The effect of the application of an interfacing (adhesive) layer is also the topic of the investigations. The physics of processing using a wavelength range from the far infrared radiation of the CO2 laser till the UV wavelengths of frequency quadrupled Nd:YAG lasers are considered to be modeled, examined and evaluated

Thick-Film and LTCC Passive Components for High-Temperature Electronics

At this very moment an increasing interest in the field of high-temperature electronics is observed. This is a result of development in the area of wide-band semiconductors’ engineering but this also generates needs for passives with appropriate characteristics. This paper presents fabrication as well as electrical and stability properties of passive components (resistors, capacitors, inductors) made in thick-film or Low-Temperature Co-fired Ceramics (LTCC) technologies fulfilling demands of high-temperature electronics. Passives with standard dimensions usually are prepared by screen-printing whereas combination of standard screen-printing with photolithography or laser shaping are recommenced for fabrication of micropassives. Attainment of proper characteristics versus temperature as well as satisfactory long-term high-temperature stability of micropassives is more difficult than for structures with typical dimensions for thick-film and LTCC technologies because of increase of interfacial processes’ importance. However it is shown that proper selection of thick-film inks together with proper deposition method permit to prepare thick-film micropassives (microresistors, air-cored microinductors and interdigital microcapacitors) suitable for the temperature range between 150°C and 400°C

Active and passive component embedding into low-cost plastic substrates aimed at smart system applications

The technology development for a low-cost, roll-to-roll compatible chip embedding process is described in this paper. Target applications are intelligent labels and disposable sensor patches. Two generations of the technology are depicted. In the first version of the embedding technology, the chips are embedded in an adhesive layer between a copper foil and a PET film. While this results in a very thin (< 200 µm) and flexible system, the single-layer routing and the incompatibility with passive components restricts the application of this first generation. The double-sided circuitry embedding technology is an extension of the single-sided, foil-based chip embedding, where the PET film is replaced by a second metal foil. To obtain sufficient mechanical strength and to further reduce cost, the adhesive film is replaced by a substrate material which is compatible with the chip embedding concept. Both versions of the foil-based embedding technology are very versatile, as they are compatible with a broad range of polymer materials, for which the specifications can be tuned to the final application

Report of the sensor readout electronics panel

The findings of the Sensor Readout Electronics Panel are summarized in regard to technology assessment and recommended development plans. In addition to two specific readout issues, cryogenic readouts and sub-electron noise, the panel considered three advanced technology areas that impact the ability to achieve large format sensor arrays. These are mega-pixel focal plane packaging issues, focal plane to data processing module interfaces, and event driven readout architectures. Development in each of these five areas was judged to have significant impact in enabling the sensor performance desired for the Astrotech 21 mission set. Other readout issues, such as focal plane signal processing or other high volume data acquisition applications important for Eos-type mapping, were determined not to be relevant for astrophysics science goals

Thermo-mechanical analysis of flexible and stretchable systems

This paper presents a summary of the modeling and technology developed for flexible and stretchable electronics. The integration of ultra thin dies at package level, with thickness in the range of 20 to 30 μ m, into flexible and/or stretchable materials are demonstrated as well as the design and reliability test of stretchable metal interconnections at board level are analyzed by both experiments and finite element modeling. These technologies can achieve mechanically bendable and stretchable subsystems. The base substrate used for the fabrication of flexible circuits is a uniform polyimide layer, while silicones materials are preferred for the stretchable circuits. The method developed for chip embedding and interconnections is named Ultra Thin Chip Package (UTCP). Extensions of this technology can be achieved by stacking and embedding thin dies in polyimide, providing large benefits in electrical performance and still allowing some mechanical flexibility. These flexible circuits can be converted into stretchable circuits by replacing the relatively rigid polyimide by a soft and elastic silicone material. We have shown through finite element modeling and experimental validation that an appropriate thermo mechanical design is necessary to achieve mechanically reliable circuits and thermally optimized packages

Contamination Control in Hybrid Microelectronic Modules. Part 1: Identification of Critical Process and Contaminants

Various hybrid processing steps, handling procedures, and materials are examined in an attempt to identify sources of contamination and to propose methods for the control of these contaminants. It is found that package sealing, assembly, and rework are especially susceptible to contamination. Moisture and loose particles are identified as the worst contaminants. The points at which contaminants are most likely to enter the hybrid package are also identified, and both general and specific methods for their detection and control are developed. In general, the most effective controls for contaminants are: clean working areas, visual inspection at each step of the process, and effective cleaning at critical process steps. Specific methods suggested include the detection of loose particles by a precap visual inspection, by preseal and post-seal electrical testing, and by a particle impact noise test. Moisture is best controlled by sealing all packages in a clean, dry, inert atmosphere after a thorough bake-out of all parts

High yield fabrication process for 3D-stacked ultra-thin chip packages using photo-definable polyimide and symmetry in packages

Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach. At first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination. Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge and thus the whole packages is named as “Flat-UTCP”. In addition to that, randomness in non-functional package positions per panel reduces the overall yield of the whole process up to certain extent. A detailed analysis on these two issues to improve the process yield is presented in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept for enhancing the fabrication yield

Warpage issues in large area mould embedding technologies

The need for higher communications speed, heterogeneous integration and further miniaturisation have increased demand in developing new 3D integrated packaging technologies which include wafer-level moulding and chip-to-wafer interconnections . Wafer-level moulding refers to the embedding of multiple chips or heterogeneous systems on the wafer scale. This can be achieved through a relatively new technology consisting of thermal compression moulding of granular or liquid epoxy moulding compounds. Experimental measurements from compression moulding on 8” blank wafers have shown an unexpected tendency to warp into a cylindrical-shape following cooling from the moulding temperature to room temperature. Wafer warpage occurs primarily as a result of a mismatch between the coefficient of thermal expansion of the resin compound and the Si wafer. This paper will delve into possible causes of such asymmetric warpage related to mould, dimensional and material characteristics using finite element (FE) software (ANSYS Mechanical). The FE model of the resin on wafer deposition will be validated against the measurement results and will be used to deduce appropriate guidelines for low warpage wafer encapsulation.peer-reviewe